MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 94

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Monitor ROM (MON)
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
7.5 ROM-Resident Routines
Eight routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory
manipulation. Six of the eight routines are intended to simplify FLASH program, erase, and load
operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM.
Table 7-10
94
shows a summary of the ROM-resident routines.
PTB0
V
RST
NOTES:
The MCU does not transmit a break character until after the host sends the
eight security bytes.
DD
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
FROM HOST
FROM MCU
Figure 7-7. Monitor Mode Entry Timing
4096 + 32 ICLK CYCLES
24 BUS CYCLES
1
NOTE
4
1
1
2
4
Freescale Semiconductor
1