MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 29

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
$0029
$002A
Addr.
$002B
$002F
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0030
$0031
$0032
$0033
$0034
↓
U = Unaffected
TIM2 Status and Control
TIM1 Channel 0 Status
TIM1 Channel 1 Status
TIM1 Counter Register
TIM2 Counter Register
TIM2 Counter Register
TIM1 Counter Modulo
TIM2 Counter Modulo
TIM2 Counter Modulo
and Control Register
and Control Register
TIM Counter Modulo
Register Name
TIM1 Channel 0
TIM1 Channel 0
TIM1 Channel 1
TIM1 Channel 1
Unimplemented
Register High
Register High
Register High
Register High
Register Low
Register Low
Register Low
Register Low
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(T2MODH)
(T1MODL)
(T2MODL)
(T2CNTH)
(T1CH0H)
(T1CH1H)
(T1CNTL)
(T2CNTL)
(TMODH)
(T1CH0L)
(T1CH1L)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
(T1SC0)
(T1SC1)
Register
(T2SC)
High
Low
Low
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CH0F
CH1F
Bit15
Bit15
Bit15
Bit15
Bit15
Bit 7
TOF
X = Indeterminate
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
0
0
0
0
1
1
0
0
0
0
0
1
1
CH0IE
CH1IE
Bit14
Bit14
Bit14
TOIE
Bit14
Bit14
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
6
0
1
1
0
0
0
0
0
1
1
TSTOP
MS0B
Bit13
Bit13
Bit13
Bit13
Bit13
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
0
5
0
1
1
0
0
1
0
0
1
1
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
= Unimplemented
MS0A
MS1A
TRST
Bit12
Bit12
Bit12
Bit12
Bit12
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
0
4
0
1
1
0
0
0
0
0
1
1
ELS0B
ELS1B
Bit11
Bit11
Bit11
Bit11
Bit11
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
3
0
1
1
0
0
0
0
0
0
1
1
ELS0A
ELS1A
Bit10
Bit10
Bit10
Bit10
Bit10
PS2
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
R
2
0
1
1
0
0
0
0
0
1
1
= Reserved
TOV0
TOV1
PS1
Bit1
Bit9
Bit1
Bit9
Bit1
Bit9
Bit1
Bit9
Bit1
Bit9
Bit1
1
0
1
1
0
0
0
0
0
1
1
Monitor ROM
CH0MAX
CH1MAX
Bit 0
PS0
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
0
1
1
0
0
0
0
0
1
1
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