MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 142

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Serial Communications Interface (SCI)
9.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
BKF — Break Flag Bit
RPF — Reception in Progress Flag Bit
9.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
R7/T7–R0/T0 — Receive/Transmit Data Bits
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This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin
followed by another break character. Reset clears the BKF bit.
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
Reading the SCDR accesses the read-only received data bits, R[7:0]. Writing to the SCDR writes the
data to be transmitted, T[7:0]. Reset has no effect on the SCDR.
1 = Break character detected
0 = No break character detected
1 = Reception in progress
0 = No reception in progress
Break character detected
Incoming data
Address:
Address:
Do not use read/modify/write instructions on the SCI data register.
Reset:
Reset:
Read:
Read:
Write:
Write:
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Bit 7
Bit 7
R7
T7
0
Figure 9-14. SCI Status Register 2 (SCS2)
= Unimplemented
Figure 9-15. SCI Data Register (SCDR)
R6
T6
6
0
6
R5
T5
5
0
5
NOTE
Unaffected by reset
R4
T4
4
0
4
R3
T3
3
0
3
R2
T2
2
0
2
BKF
R1
T1
1
0
1
Freescale Semiconductor
Bit 0
RPF
Bit 0
R0
T0
0