MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 145

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 10
Analog-to-Digital Converter (ADC)
10.1 Introduction
This section describes the 13-channel, 8-bit linear successive approximation analog-to-digital converter
(ADC).
10.2 Features
Features of the ADC module include:
10.3 Functional Description
Thirteen ADC channels are available for sampling external sources at pins PTB0–PTB7, PTD0–PTD3,
and ADC12/T2CLK. An analog multiplexer allows the single ADC converter to select one of the 13 ADC
channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation
register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the
result in the ADC data register and sets a flag or generates an interrupt.
Figure 10-2
Freescale Semiconductor
Addr.
$003C
$003D
$003E
•
•
•
•
•
13 channels with multiplexed input
Linear successive approximation with monotonicity
8-bit resolution
Single or continuous conversion
Conversion complete flag or conversion complete interrupt
ADC Input Clock Register
ADC Status and Control
Register Name
shows a block diagram of the ADC.
ADC Data Register
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(ADICLK)
(ADSCR)
Register
(ADR)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 10-1. ADC I/O Register Summary
COCO
ADIV2
Bit 7
AD7
0
0
ADIV1
AIEN
AD6
6
0
0
ADCO
ADIV0
AD5
5
0
0
Indeterminate after reset
ADCH4
AD4
4
1
0
0
ADCH3
AD3
3
1
0
0
ADCH2
AD2
2
1
0
0
ADCH1
AD1
1
1
0
0
ADCH0
Bit 0
AD0
1
0
0
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