MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 27

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Addr.
$000C
$000D
$000A
$000B
$000E
$000F
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$0012
↓
U = Unaffected
Port D Data Register (PTD)
Port A Data Register (PTA)
Port B Data Register (PTB)
Port D Control Register
Data Direction Register D
Data Direction Register A
Data Direction Register B
Data Direction Register E
Register Name
Port A Input Pull-up
Port E Data Register
PTA7 Input Pull-up
Enable Register
Enable Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(PTA7PUE)
(PTAPUE)
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
(PDCR)
(DDRD)
(DDRA)
(DDRB)
(DDRE)
(PTE)
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
PTAPUE7
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
DDRA7
DDRB7
DDRD7
PTD7
PTA7
PTB7
Bit 7
X = Indeterminate
0
0
0
0
0
0
0
0
DDRA6
DDRB6
DDRD6
PTD6
PTA6
PTB6
0
6
0
0
0
0
0
0
0
DDRA5
DDRB5
DDRD5
PTD5
PTA5
PTB5
0
5
0
0
0
0
0
0
0
= Unimplemented
DDRA4
DDRB4
DDRD4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
PTA4
PTB4
PTD4
0
4
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7
DDRD3
DDRA3
DDRB3
PTA3
PTB3
PTD3
3
0
0
0
0
0
0
0
DDRD2
DDRA2
DDRB2
PTA2
PTB2
PTD2
R
2
0
0
0
0
0
0
0
= Reserved
DDRD1
DDRA1
DDRB1
DDRE1
PTA1
PTB1
PTD1
PTE1
1
0
0
0
0
0
0
0
Monitor ROM
PTDPU6
DDRA0
DDRB0
DDRD0
DDRE0
PTA0
PTB0
PTD0
PTE0
Bit 0
0
0
0
0
0
0
0
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