MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 71

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

5.5.2.1 Interrupt Status Register 1
IF1, IF3 to IF6 — Interrupt Flags
Bit 0, 1, and 3 — Always read 0
Freescale Semiconductor
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
These flags indicate the presence of interrupt requests from the sources shown in
Priority
Highest
Lowest
1 = Interrupt request present
0 = No interrupt request present
Reset
SWI Instruction
IRQ Pin
Timer 1 Channel 0 Interrupt
Timer 1 Channel 1 Interrupt
Timer 1 Overflow Interrupt
Timer 2 Channel 0 Interrupt
Timer 2 Channel 1 Interrupt
Timer 2 Overflow Interrupt
SCI Error
SCI Receive
SCI Transmit
Keyboard Interrupt
ADC Conversion Complete Interrupt
Address:
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
$FE04
Bit 7
IF6
R
R
0
Source
Figure 5-12. Interrupt Status Register 1 (INT1)
= Reserved
IF5
R
6
0
Table 5-3. Interrupt Sources
IF4
R
5
0
COCO
IF3
SCRF
CH0F
CH1F
CH0F
CH1F
SCTE
KEYF
R
IRQF
4
0
IDLE
Flag
TOF
TOF
OR
NF
FE
PE
TC
—
—
R
3
0
0
IMASKK
Mask
IMASK
CH0IE
CH1IE
CH0IE
CH1IE
SCRIE
SCTIE
ORIE
TOIE
TOIE
NEIE
PEIE
TCIE
AIEN
FEIE
ILIE
—
—
(1)
IF1
R
2
0
INT Flag
IF11
IF12
IF13
IF14
IF15
IF1
IF3
IF4
IF5
IF6
IF8
IF7
—
—
R
1
0
0
Table
Bit 0
R
Vector Address
0
0
Exception Control
$FFEC–$FFED
$FFDE–$FFDF
$FFFC–$FFFD
$FFEE–$FFEF
$FFFE–$FFFF
$FFFA–$FFFB
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
5-3.
71