MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 67

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
5.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of ICLK.
5.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
5.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay
of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that
do not require long start-up times from stop mode. External crystal applications should use the full stop
recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1).
5.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See
free-running after all reset states. (See
internal reset recovery sequences.)
5.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 5-8
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
Freescale Semiconductor
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Interrupts
–
–
Reset
Break interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
flow charts the handling of system interrupts.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
5.3.2 Active Resets from Internal Sources
5.6.2 Stop Mode
for details.) The SIM counter is
for counter control and
SIM Counter
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