MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 66

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

System Integration Module (SIM)
OSC1
PORRST
4096
32
32
CYCLES
CYCLES
CYCLES
ICLK
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 5-7. POR Recovery
5.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the
RST pin for all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at
12
4
least every (2
– 2
) ICLK cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor
TST
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, V
on the RST pin disables the COP module.
TST
5.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the reset status register (RSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction
as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
5.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down
the RST pin for all internal reset sources.
5.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
voltage falls to the LVI
DD
trip voltage V
. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is
TRIP
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
66
Freescale Semiconductor