MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 89

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

When the host computer has completed downloading code into the MCU RAM, the host then sends a
RUN command, which executes an RTI, which sends control to the address on the stack pointer.
7.3.2 Baud Rate
The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud
rate if entry to monitor mode is by IRQ = V
pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.
7.3.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
(See
Freescale Semiconductor
Figure 7-3
BREAK
Monitor
Modes
$A5
Notes:
1. If the high voltage (V
User
and
Blank reset vector,
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
START
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit
in the configuration register.
Monitor Mode
BIT
IRQ = V
IRQ = V
Entry By:
START
START
Figure
BIT
BIT
BIT 0
Disabled
Enabled
TST
DD
COP
BIT 0
BIT 0
7-4.)
Table 7-2. Monitor Mode Vector Differences
BIT 1
Figure 7-4. Sample Monitor Waveforms
Table 7-3. Monitor Baud Rate Selection
(1)
BIT 1
BIT 1
TST
Figure 7-3. Monitor Data Format
BIT 2
Vector
$FFFE
$FEFE
Reset
) is removed from the IRQ pin or the RST pin, the SIM asserts
High
BIT 2
BIT 2
OSC1 Clock
4.9152 MHz
9.8304 MHz
4.9152 MHz
9.8304 MHz
4.9152 MHz
Frequency
TST
BIT 3
. When PTB3 is high, the divide by ratio is 1024. If the PTB3
BIT 3
BIT 3
Vector
$FFFF
$FEFF
Reset
Low
BIT 4
BIT 4
BIT 4
Functions
BIT 5
Vector
$FFFC
$FEFC
Break
High
BIT 5
BIT 5
PTB3
X
X
0
1
1
BIT 6
BIT 6
BIT 6
Vector
$FFFD
$FEFD
Break
Low
BIT 7
BIT 7
BIT 7
STOP
BIT
Baud Rate
$FEFC
9600 bps
9600 bps
4800 bps
9600 bps
4800 bps
Vector
$FFFC
STOP
STOP
High
BIT
BIT
SWI
START
NEXT
BIT
START
START
NEXT
NEXT
BIT
BIT
Vector
$FFFD
$FEFD
Functional Description
Low
SWI
89