MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 155

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

11.2.3 Port A Input Pull-Up Enable Registers
The port A input pull-up enable registers contain a software configurable pull-up device for each of the
eight port A pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRAx be configured as input. Each pull-up device is automatically disabled when its
corresponding DDRAx bit is configured as output.
PTA6EN — Enable PTA6 on OSC2
PTAPUE[7:0] — Port A Input Pull-up Enable Bits
Freescale Semiconductor
This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has
no effect for XTAL oscillator option.
These read/write bits are software programmable to enable pull-up devices on port A pins.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Figure 11-6. PTA7 Input Pull-up Enable Register (PTA7PUE)
Figure 11-5. Port A Input Pull-up Enable Register (PTAPUE)
PTAPUE7
PTA6EN
$000D
$000E
Bit 7
Bit 7
0
0
PTAPUE6
6
0
6
0
PTAPUE5
5
0
5
0
PTAPUE4
4
0
4
0
PTAPUE3
3
0
3
0
PTAPUE2
2
0
2
0
PTAPUE1
1
0
1
0
PTAPUE0
Bit 0
Bit 0
0
0
Port A
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