MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 190

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Electrical Specifications
17.9 3V Control Timing
190
Capacitance
POR rearm voltage
POR rise time ramp rate
Monitor mode entry voltage
Pullup resistors
Low-voltage inhibit, trip voltage
(No hysteresis implemented for 3V LVI)
Internal operating frequency
RST input pulse width low
TIM2 external clock input
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. Stop I
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
8. R
1. V
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
Ports (as input or output)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
Less than 100 pF on all outputs. C
run I
100 pF on all outputs. C
V
noted.
DD
PU1
DD
DD
= 2.7 to 3.3 Vdc, V
DD
is reached.
= 2.7 to 3.3 Vdc, V
DD
and R
DD
. Measured with all modules enabled.
measured using external square wave clock source (f
measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
(8)
PU2
DD
(6)
are measured at V
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Characteristic
RST
IRQ
measured using external square wave clock source (f
(7)
(2)
(3)
Characteristic
SS
SS
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
= 0 Vdc, T
= 0 Vdc, T
Table 17-7. DC Electrical Characteristics (3V)
(1)
DD
L
A
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
A
= 5.0V.
Figure 17-3. RST and IRQ Timing
(1)
= T
= T
Table 17-8. Control Timing (3V)
L
L
(3)
to T
to T
H
t
H
t
ILIH
RL
, unless otherwise noted.
; timing shown with respect to 20% V
t
ILIL
Symbol
OP
C
V
R
R
R
V
V
C
POR
OUT
POR
LVI3
TST
PU1
PU2
= 4MHz). All inputs 0.2V from rail. No dc loads. Less than
IN
Symbol
f
T2CLK
OP
t
t
f
t
ILIH
ILIL
OP
RL
1.5 × V
= 4MHz). All inputs 0.2V from rail. No dc loads.
0.035
Min
2.18
1.8
16
—
—
0
DD
Note
DD
Min
200
1.5
—
—
and 70% V
(4)
Typ
2.49
3.3
26
—
—
—
—
—
(2)
Freescale Semiconductor
CYC
Max
DD
—
—
—
4
2
, unless otherwise
.
Max
100
2.68
8.5
4.8
12
—
36
8
MHz
MHz
Unit
t
CYC
DD
µs
ns
V/ms
Unit
mV
kΩ
kΩ
pF
.
V
V