MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 139

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
9.8.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
Freescale Semiconductor
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables SCI error CPU interrupt
requests generated by the parity error bit, PE.
(See
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This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
9.8.4 SCI Status Register
Address:
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
SCTE
$016
Bit 7
1
Figure 9-12. SCI Status Register 1 (SCS1)
= Unimplemented
TC
6
1
1.) Reset clears PEIE.
SCRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
PE
0
I/O Registers
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