MC68HC908JK8CP Freescale Semiconductor, MC68HC908JK8CP Datasheet - Page 174

• Manufacturer Part Number: MC68HC908JK8CP
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908JK8CP

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 13-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
2
configuration register 1. Writing any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
A COP reset pulls the RST pin low for 32 × ICLK cycles and sets the COP bit in the reset status register
(RSR). (See
14.3 I/O Signals
The following paragraphs describe the signals shown in
14.3.1 ICLK
ICLK is the internal oscillator output signal, typically 50-kHz. The ICLK frequency varies depending on the
supply voltage. See Chapter 17 Electrical Specifications for ICLK parameters.
14.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 14.4 COP Control Register) clears the
COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns
the low byte of the reset vector.
14.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × ICLK cycles after power-up.
14.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
14.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
14.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1
(CONFIG1). (See
174
18
– 2
4
or 2
13
5.7.2 Reset Status Register
– 2
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
4
Chapter 3 Configuration and Mask Option Registers (CONFIG &
ICLK cycles; depending on the state of the COP rate select bit, COPRS, in
(RSR).).
NOTE
NOTE
Figure
14-1.
Freescale Semiconductor
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