XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 127

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Table 4 describes the role of these signals when the Microprocessor Interface is operating in the Motorola
Mode.
Table 2 Description of the Microprocessor Interface Signals that exhibit constant roles in both the
“Intel” and “Motorola” Modes.
Table 3 Pin Description of Microprocessor Interface Signals - While the Microprocessor Interface is
Operating in the Intel Mode.
WRB_RW
Rdy_Dtck
P
RdB_DS
ALE_AS
IN
P
A[14:0]
IN
D[7:0]
N
INT*
CS*
AME
N
AME
E
QUIVALENT
E
T
NVIRONMENT
I/O
YPE
O
READY*
I
I
WR*
ALE
RD*
P
IN IN
Bi-Directional Data Bus for register read or write operations.
This byte wide carries all data that is being written into or read from the XRT94L33.
Fourteen Bit Address Bus input:
This nine bit Address Bus is provided to allow the user to select an on-chip register or on-chip
RAM location.
Chip Select input.
This “active low” signal selects the Microprocessor Interface of the XRT94L33 and enables
read/write operations with the on-chip registers/on-chip RAM.
Interrupt Request Output
This “open-drain/active-low” output signal will inform the local µP that the XRT94L33 has an
interrupt condition that needs servicing.
I
NTEL
T
YPE
O
I
I
I
Address-Latch Enable: This “active-high” signal is used to latch the
contents on the address bus, A[8:0]. The contents of the Address Bus are
latched into the A[8:0] inputs on the falling edge of ALE_AS. Additionally,
this signal can be used to indicate the start of a burst cycle.
Read Signal: This “active-low” input functions as the read signal from the
local µP. When this signal goes “low”, the XRT94L33 Microprocessor
Interface will place the contents of the addressed register on the Data Bus
pins (D[7:0]). The Data Bus will be “tri-stated” once this input signal
returns “high”.
Write Signal: This “active-low” input functions as the write signal from the
local µP. The contents of the Data Bus (D[7:0]) will be written into the
addressed register (via A[8:0]), on the rising edge of this signal.
Ready Output: This “active-low” signal is provided by the XRT94L33, and
indicates that the current read or write cycle is to be extended until this
signal is asserted. The local µP will typically insert “WAIT” states until this
signal is asserted. This output will toggle “low” when the device is ready
for the next Read or Write cycle.
127
D
ESCRIPTION
D
ESCRIPTION
XRT94L33
Rev.1.2.0.