XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 141

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
STEP 2 – INTERRUPT SERVICE ROUTING BRANCHING: AFTER READING THE OPERATION BLOCK
INTERRUPT STATUS REGISTERS
The contents of the Operation Block Interrupt Status Registers permit the user to identify which of the seven
(7) functional blocks (within the XRT94L33 IC) have requested interrupt service. The µP/µC should use this
information in order to determine where, within the Interrupt Service Routine, program control should branch
to. The following table can be viewed as an “interrupt service routine” guide. It lists each of the Functional
Blocks that contain bit-field in the Operation Block Interrupt Status and Enable registers. Additionally, this
table also presents a list and addresses of the corresponding on-chip Registers that the Interrupt Service
Routine should branch to and read; based upon the Interrupt Functional Block.
Table 9 Interrupt Service Routine Guide for the XRT94L33
Operation Control Block
Receive ATM Cell Processor
Block
Receive SONET/STS-3c POH
Processor Block
Receive
Processor Block
Receive
Processor Block
Transmit ATM Cell Processor
Block
Transmit
Processor Block
DS3/E3 Mapper Block
DS3/E3 Framer Block
Note:
Once the µC/µP has read out the contents of the appropriate register (as listed above in Table 9); then there
may (or may not) be additional “interrupt status” registers to read; as described below.
Interrupt Servicing for the “Operation Control” Block
If the interrupt service routine is currently servicing an “Operation Control” Block Interrupt, then reading out
the contents of the corresponding register (as presented in Table 9) should result in the following
occurrences.
I
NTERRUPTING
1. The µC/µP will uniquely identify the source or condition causing the interrupt request.
2. The “asserted interrupt status” bit-fields within this register will be reset upon read.
3. The “asserted” bit-field(s), within the Operation Block Interrupt Status Register will be reset.
Registers associated within each functional block are specified in ascending order (based upon the on-chip
Address Location). No other inferences should be made regarding the order in which these registers are
presented in this table.
B
LOCK
PPP
STS-3
PPP
F
UNCTIONAL
Packet
Packet
TOH
Operation Interrupt Status Register – Byte 0
Operation Channel Interrupt Indicator – Receive ATM Cell Processor
Block
Operation Channel Interrupt Indicator – Receive SONET POH
Processor Block
Receive STS-3 Transport Interrupt Status Register – Byte 2
Receive STS-3 Transport Interrupt Status Register – Byte 1
Receive STS-3 Transport Interrupt Status Register – Byte 0
Operation Channel Interrupt Indicator – Receive PPP Packet
Processor Block
Operation Channel Interrupt Indicator – Transmit ATM Cell Processor
Block
Operation Channel Interrupt Indicator – Transmit PPP Packet
Processor Block
Operation Channel Interrupt Indicator – DS3/E3 Mapper Block
Operation Channel Interrupt Indicator – DS3/E3 Framer Block
T
HE
N
EXT
R
EGISTER TO BE
141
R
R
EAD
OUTINE
D
URING THE
I
NTERRUPT
S
ERVICE
XRT94L33
L
A
0x010B
0x0128
0x0120
0x1109
0x110A
0x110B
0x012A
0x0127
0x0129
0x0126
0x0122
OCATION
DDRESS
Rev.1.2.0.