XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 379

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
•
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
SF DECLARATION CRITERIA – per the “Burst” SF Detector
In this case, the user specifies two parameters to define the SF Declaration criteria.
• The minimum number of B2 errors (e.g., a B2 error-threshold) accumulated over a given “SF Set Interval”
time period.
• The length (in terms of SONET frame periods) of this “SF Set Interval” time period.
Once the user defines these parameters, then the Receive STS-3 TOH Processor block will begin to count
the cumulative number of B2 errors that it detects within a “sliding window” of time. The length of this “sliding
window of time” is dictated by the user-defined “SF Set Interval” time period.
As long as the Receive STS-3 TOH Processor block does not detects the “B2 error threshold” number of B2
errors, within this “SF Set Interval” of time, then it will not declare the SF Condition. Conversely, if the
Receive STS-3 TOH Processor block detects at least the “B2 error threshold” number of B2 errors, within the
“SF Set Interval” of time, then it will declare the SF Condition.
Specifying the “B2 Error Threshold” for Declaring SF
The user can specify the “B2 Error Threshold” by writing the appropriate value into the “Receive STS-3
Transport – Receive SF Burst Error Tolerance – Byte 1 and Byte 0” registers, as depicted below.
Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address = 0x1156)
Change of
Condition
Declared
Interrupt
Status
RDI-L
B
B
B
RUR
R/W
It will set Bit 4 (SF Detected) within the “Receive STS-3 Transport Status Register – Byte 0” to “0”,
as depicted below.
R/O
SF
IT
IT
IT
1
0
1
7
7
7
S1 Unstable
Change of
Condition
Interrupt
Status
B
RUR
B
B
R/W
R/O
SD
IT
IT
IT
0
0
1
6
6
6
REI-L Error
Unstable
Interrupt
Status
B
RUR
B
B
APS
R/W
R/O
IT
IT
IT
0
0
1
5
5
5
SF_BURST_TOLERANCE[15:8]
SF Detected
B2 Error
Interrupt
Status
B
RUR
B
B
R/W
R/O
IT
IT
IT
0
0
1
4
4
4
379
SD Detected
B1 Error
Interrupt
Status
B
RUR
B
B
R/W
R/O
IT
IT
IT
0
0
1
3
3
3
LOF Defect
Change of
Condition
Detected
Interrupt
Status
B
RUR
B
B
LOF
R/W
R/O
IT
IT
IT
0
0
1
2
2
2
SEF Defect
Declared
Interrupt
Status
B
RUR
B
B
SEF
R/W
R/O
IT
IT
IT
0
0
1
1
1
1
XRT94L33
LOS Defect
Change of
Condition
Declared
Interrupt
Status
Rev.1.2.0.
B
RUR
B
B
LOS
R/W
R/O
IT
IT
IT
0
0
1
0
0
0