XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 268

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.2.8.3.3.3
The user can configure the Transmit SONET POH Processor block to transmit the REI-P (per the external
input port) by executing the following steps.
STEP 1 – Write the value [1, 0] into Bits 3 and 4 (REI-P Insertion Type[1:0]) within the “Transmit
SONET Path – SONET Control Register – Byte 0” as depicted below.
Transmit SONET Path – SONET Control Register – Byte 0 (Address = 0xN983)
This step configures the Transmit SONET POH Processor block to set the value of the REI-P bit-fields (within
the outbound STS-1 SPE) based upon the data that it receives via the “TxPOH_n” input port. In this mode,
the Transmit SONET POH Processor block will accept the value corresponding to the REI-P fields (via the
“TxPOH_n Input Port”) and it will write this data into the “outbound” STS-1 SPE data-stream.
STEP 2 – Begin providing the values of the “outbound” REI-P bit-fields to the “TxPOH_n” input port.
The procedure for applying the REI-P bit-values to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the REI-P bit values into the outbound STS-1 SPE data-stream
If the user intends to externally insert the REI-P bits into the outbound STS-1 SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do the following.
•
•
F2 Insertion
B
Type
R/W
Continuously sample the “TxPOHEnable_n” and the “TxPOHEnable_n” output pins upon the rising edge
of the “TxPOHClk_n” output clock signal.
Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it waits for 28 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit of
the “outbound” REI-P bit-fields onto the “TxPOH_n” input pin, upon the very next falling edge of
“TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit SONET POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”
IT
0
7
REI-P Insertion Type[1:0]
Configuring the Transmit SONET POH Processor block to transmit the REI-P indicator,
via the “TxPOH_n” input port
B
R/W
IT
1
6
B
R/W
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
RDI-P Insertion Type[1:0]
B
R/W
IT
0
4
268
B
R/W
IT
0
3
Insertion
C2 Byte
B
Type
R/W
IT
0
2
Auto Insert
C2 Byte
Enable
Mode
B
R/W
IT
0
1
xr
Transmit
Enable
AIS-P
B
R/W
IT
0
0