XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 289
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 55: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for _ periods of “TxPOHClk_n” to elapse).
Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g., the most
significant bit) of the “outbound” Z4 byte onto the “TxPOH_n” input pin, upon the very next falling edge of
“TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit SONET POH Processor” block
circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the H4 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
2.2.8.3.10
The Transmit SONET POH Processor block permits the user to control the value of the H4 byte by either of
the following options.
• Setting and controlling the “outbound” Z5 Byte via Software
• Setting and controlling the “outbound” Z5 Byte via the “TxPOH Input Port”
The details and instructions for using either or these features are presented below.
2.2.8.3.10.1
The Transmit SONET POH Processor block permits the user to specify the contents of the Z5 byte, within the
“outbound” STS-1 SPE via software command.
The “TxPOHIns_n” line (inFigure 55) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the Z4 byte is the 8th byte within the POH.
executed “STEP 1” above.
SUPPORT/HANDLING OF THE Z5 BYTE
Setting and Controlling the Outbound Z5 Byte via Software
XRT95L34 Device
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
289
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
XRT94L33
Rev.1.2.0.
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