XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 332

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
• It will detect and flag REI-P events
• It will detect and clear the UNEQ-P, PLM-P and TIM-P conditions
• It will declare and clear the LOP-C and AIS-C conditions.
Finally, the Receive STS-3c POH Processor block will extract out the payload data from each incoming STS-
3c SPE, and will route this data to either the Receive ATM Cell Processor block (for ATM UNI applications) or
the Receive PPP Packet Processor block (for PPP applications).
For ATM Applications
The Receive ATM Cell Processor block will receive a continuous stream of un-framed ATM cells, and will
perform the following functions on this incoming data-stream.
• Cell Delineation
• HEC Byte Verification
• Idle Cell Filtering
• User Cell Filtering
• Parity Calculation and Insertion
Afterwards, the Receive ATM Cell Processor block will route all cells (which have satisfactorily survived the
above-mentioned processing) to the Rx FIFO, within the Receive UTOPIA Interface block.
The ATM Layer Processor will read out the contents of these ATM cells via the Receive UTOPIA Interface
block of the XRT94L33. The Receive UTOPIA Interface block provides the industry-standard ATM/PHY
interface functions. The Receive UTOPIA Interface block will also provide signaling to support data-flow
control between the ATM Layer Processor and the Receive UTOPIA Interface block.
The Receive Section of the XRT94L33 is discussed in considerable detail below.
For PPP Applications
The Receive PPP Packet Processor block will receive a continuous stream of un-framed PPP packets, and
will perform the following functions on this incoming data-stream.
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•
2.3.1
The purpose of the Receive STS-3 TOH Processor block is to accomplish the following.
• To receive an STS-3 data-stream from the remote LTE, via an Optical Transceiver or the System Back-
plane (through the Receive PECL Interface) or via the Receive STS-3 Telecom Bus Interface.
• To acquire and maintain frame synchronization with the incoming STS-3 data-stream
• To optionally de-scramble the incoming STS-3 data-stream.
• To compute and verify the B1 and B2 bytes and increment performance monitor registers anytime it detects
B1 and B2 byte errors.
• To declare and clear the following defect conditions
CRC-16/32 Checking
Byte-De-Stuffing
RECEIVE STS-3 TOH PROCESSOR BLOCK
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LOS (Loss of Signal)
SEF (Severely Errored Frame)
LOF (Loss of Frame)
AIS-L (Line AIS)
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
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