XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 323

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.2.9.5.9.2
The Transmit STS-3c TOH Processor block permits the user to specify the contents of the K1, K2 bytes within
the “outbound” STS-3c data-stream via the data applied to the “TxPOH_n” input port.
The user can configure the Transmit STS-3c TOH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “1” into Bit 4 (STS-3c TOH Insert) within the “Mapper Control Register – Byte
2”, as depicted below.
Mapper Control Register – Byte 2 (Direct Address = 0xN601)
This step enables the “Transmit STS-3c TOH Processor” block (associated with Channel “N”) to accept its
TOH bytes via the “TxPOH Input” port.
STEP 2 – Write the value “0” into Bit 1 (K1K2 Insert Method) within the “Transmit STS-3c Transport –
SONET Transmit Control Register – Byte 1; as depicted below.
Transmit STS-3Transport – SONET Transmit Control Register – Byte 1 (Address = 0x1902)
This step configures the Transmit STS-3c TOH Processor block to use the “TxPOH Input” port as the source
for the K1, K2 bytes, within each outbound STS-3c frame. In this mode, the Transmit STS-3c TOH Processor
block will accept the value, corresponding to the K1 and K2 bytes (via the “TxPOH_n” input port) and it will
write this data into the K1 and K2 byte positions, within the “outbound” STS-3c frame.
Using the “TxPOH_n Input” port to insert the K1 and K2 byte values into the “outbound” STS-3c data-
stream
If the user intends to externally insert the K1 and K2 into the outbound STS-3c data-stream, via the
“TxPOH_n” input port, then they must design some external circuitry (which can be realized in an ASIC,
FPGA or CPLD solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 72
STS-3c OH
Pass Thru
B
B
R/W
R/O
IT
IT
0
0
7
7
Reserved
Loop-back
Setting and Controlling the outbound K1, K2 bytes via “TxPOH Input Port”
Remote
STS-3c
B
B
R/W
R/O
IT
IT
0
0
6
6
Local Loop-
E2 Insert
STS-3c
Method
B
back
B
R/W
R/W
IT
IT
X
0
5
5
TOH Insert
E1 Insert
STS-3c
Method
B
B
R/W
R/W
IT
IT
X
1
4
4
323
Loop-Timing
F1 Insert
Method
B
B
R/W
R/W
IT
IT
X
0
3
3
POH Pass
S1 Insert
Method
B
B
Thru
R/W
R/W
IT
IT
0
X
2
2
K1K2 Insert
(Ingress )
Receive
STS-3c
Method
Enable
B
B
R/W
R/W
IT
IT
0
0
1
1
XRT94L33
M0M1 Insert
Method[1]
Transmit
(Egress)
STS-3c
Enable
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
0
X
0
0