XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 398

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Receive SONET Path – SONET Receive Path Interrupt Status – Byte 0 (Address = 0xN18B)
Note:
Configuring the Receive SONET POH Processor block to increment the “Receive SONET Path – B3
Error Count” register on a “per B3 bit-error” basis
The user can configure the Receive SONET POH Processor block to increment the “Receive SONET Path –
B3 Error Count” Register by the number of “B3 bits” which are determined to be in error. Therefore, in this
mode, it is possible for the Receive SONET POH Processor block to increment this register by as much as
the value of “8” per STS-1 SPE.
The user can accomplish this by setting Bit 0 (B3 Error Type) within the “Receive SONET Path – Control
Register – Byte 0” to “0”, as illustrated below.
Receive SONET Path – Control Register – Byte 0 (Address = 0xN183)
Note:
The detection of B3 byte errors also plays a role in the transmission of the REI-P (Path – Remote Error
Indicator) back out to the Remote Terminal Equipment. This item will be discussed in some detail in Section
_.
Detection of
Interrupt
B3 Byte
Status
B
Error
RUR
B
b. It will increment the “Receive SONET Path – B3 Error Count” registers. The “Receive SONET Path –
R/O
IT
IT
1
0
7
7
B3 Error Count” register is actually a 32 bit register that resides at Direct Address 0xNA98 – 0xNA9B.
The Receive SONET POH Processor block will increment these registers either by the number of erred STS-1
If the user implements this setting, then the corresponding Transmit SONET POH Processor block will set the
SPEs detected, or by the number of B3 bits that are detected to be in error (within a given STS-1 frame),
depending upon user selection, as described below.
REI-P nibble value (within the G1 byte) to the number of B3 bits that have been determined to be in error. In
this case, the REI-P nibble value can contain a number as high as “8” for each “outbound” STS-1 frame.
New Pointer
Detection of
Interrupt
Status
B
RUR
B
R/O
IT
IT
0
0
6
6
Unused
Detection of
Unknown
Interrupt
Pointer
Status
B
RUR
B
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Detection of
Decrement
Interrupt
Pointer
Status
B
B
RUR
R/O
IT
IT
0
0
4
4
398
Detection of
Increment
Interrupt
Pointer
Status
Check
B
RUR
B
Stuff
R/W
IT
IT
0
0
3
3
NDF Pointer
Detection of
Interrupt
Status
RDI-P
B
B
Type
RUR
R/W
IT
IT
0
0
2
2
Error Type
Change of
Condition
Interrupt
LOP-P
Status
REI-P
B
RUR
B
R/W
IT
IT
0
0
1
1
xr
Change of
Condition
Interrupt
B3 Error
Status
AIS-P
Type
B
RUR
B
R/W
IT
IT
0
1
0
0