XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 167

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Table 13 UTOPIA Address Values of the UTOPIA Interface blocks illustrated in Figure 26.
Transmit UTOPIA Interface block - UNI #1
Receive UTOPIA Interface block - UNI #1
Transmit UTOPIA Interface block - UNI #2
Receive UTOPIA Interface block - UNI #2
Recall, that the Transmit UTOPIA Interface blocks were assigned these addresses by writing these values
into registers that are similar to the “Transmit UTOPIA Port Number (Address = 0x0597) and the Transmit
UTOPIA Address Register” (Address = 0x0593) within these UNI devices. The discussion of the Receive
UTOPIA Interface blocks, within UNIs #1 and #2 is presented in Section _.
Polling Operation
Consider that the ATM Layer processor is currently writing a continuous stream of ATM cell data into UNI #1.
While writing this cell data into UNI #1, the ATM Layer processor can also “poll” UNI #2 for “availability” (e.g.,
tries to determine if the ATM Layer processor can write any more ATM cell data into the “Transmit UTOPIA
Interface block” within UNI #2).
The ATM Layer processor’s role in the “polling” operation
The ATM Layer processor accomplishes this “polling” operation by executing the following steps.
1. Assert the TxUEnB* input pin (if it is not asserted already).
The UNI device (being “polled”) will know that this is only a “polling” operation, if the TxUEnB* input pin is
asserted, prior to detecting its UTOPIA Address on the “UTOPIA Address” bus (TxUAddr[4:0]).
2. The ATM Layer processor places the address of the Transmit UTOPIA Interface Block of UNI #2
onto the UTOPIA Address Bus, Ut_Addr[4:0],
3. The ATM Layer processor will then check the value of its “TxUClav_in” input pin (see Figure 24).
The ATM Layer Processor is suppose to check the state of the “TxUClav” signal, one “TxUClk” period after
placing the UTOPIA Address (corresponding to a particular UNI device) on the “TxUAddr[4:0]” input pins. If
“TxUClav” is sampled “high” then this means that this particular UNI device contains sufficient empty space
within its TxFIFO to accept another ATM cell from the ATM Layer Processor. Conversely, if TxUClav is
sampled “low” then this means that this particular UNI device does not contain enough empty space within its
TxFIFO to accept another ATM cell from the ATM Layer Processor.
The UNI devices role in the “polling” operation
UNI #2 will sample the signal levels placed on its Tx UTOPIA Address input pins (TxUAddr[4:0]) on the rising
edge of its “Transmit UTOPIA Interface block” clock input signal, TxUClk. Afterwards, UNI #2 will compare
the value of these “Transmit UTOPIA Address Bus input pin” signals with that of the contents of its “Tx
UTOPIA Address Register (Address = 0x0593).
If these values do not match, (e.g., TxUAddr[4:0] ≠ 0x02) then UNI #2 will keep its “TxUClav” output signal
“tri-stated”; and will continue to sample its “Transmit UTOPIA Address bus input” pins; with each rising edge
of TxUClk.
If these two values do match, (e.g., TxUAddr[4:0] = 0x02) then UNI #2 will drive its “TxUClav” output pin to the
appropriate level, reflecting its TxFIFO “fill-status”.
Handshaking” mode, the UNI will drive the TxUClav output signal “high” if it is capable of receiving at least
one more complete cell of data from the ATM Layer processor. Conversely, the UNI will drive the “TxUClav”
B
LOCK
167
Since the UNI is only operating in the “Cell Level
UTOPIA A
0x00
0x01
0x02
0x03
DDRESS
V
ALUE
XRT94L33
Rev.1.2.0.