XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 335

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
• It will generate the “Change of LOS Defect Condition” Interrupt, by toggling the “INT*” output pin “LOW”,
and by setting Bit 0 (Change of LOS Defect Condition Interrupt Status), within the “Receive STS-3 Transport
Interrupt Status Register – Byte 0” to “1”, as illustrated below.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.2.2
The Receive STS-3 TOH Processor block will clear the LOS defect once both of the following conditions have
been met.
That the Receive STS-3 TOH Processor block detects proper A1 and A2 bytes in two consecutive STS-3
frames, and
That, in between the detection of the two sets of A1/A2 bytes, the Receive STS-3 TOH Processor block does
not detect the “LOS_THRESHOLD[15:0]” number of “All Zero” bytes, within the incoming STS-3 data-stream.
Once the Receive STS-3 TOH Processor block clears the LOS defect, it will notify the system of this fact by
doing the following.
• It will set Bit 1 (LOS Detected) within the Receive STS-3c Transport Status Register – Byte 0” to “0” as
illustrated below.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
• It will generate the “Change of LOS Defect Condition” Interrupt by toggling the “INT*” output pin “LOW”, and
by setting Bit 0 (Change of LOS Defect Condition Interrupt Status), within the “Receive STS-3 Transport
Interrupt Status Register – Byte 0” to “1”, as illustrated below.
Change of
SF Defect
Condition
Declared
Declared
Interrupt
Defect
Defect
Status
RDI-L
RDI-L
B
B
B
RUR
R/O
R/O
IT
IT
IT
0
0
0
7
7
7
How the Receive STS-3 TOH Processor Block Clears the LOS Defect
Change of
SD Defect
Condition
Unstable
Declared
Unstable
Declared
Interrupt
S1 Byte
S1 Byte
Defect
Status
Defect
B
B
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
6
6
6
Detection of
K1, K2 Byte
K1, K2 Byte
REI-L Error
Declared
Declared
Unstable
Unstable
Interrupt
Defect
Defect
Status
B
B
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
5
5
5
Detection of
SF Defect
SF Defect
Declared
Declared
Interrupt
B2 Byte
Status
B
B
Error
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
4
4
4
335
Detection of
SD Defect
SD Defect
Declared
Declared
Interrupt
B1 Byte
Status
Error
B
B
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
3
3
3
LOF Defect
LOF Defect
LOF Defect
Change of
Condition
Declared
Declared
Interrupt
Status
B
B
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
2
2
2
SEF Defect
SEF Defect
SEF Defect
Change of
Condition
Declared
Declared
Interrupt
Status
B
B
RUR
B
R/O
R/O
IT
IT
IT
0
0
0
1
1
1
XRT94L33
LOS Defect
LOS Defect
LOS Defect
Change of
Condition
Declared
Declared
Interrupt
Status
Rev.1.2.0.
B
B
B
RUR
R/O
R/O
IT
IT
IT
1
1
0
0
0
0