XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 5

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AF22
P
IN
#
S
IGNAL
PWR_L/
R/W*
N
AME
I/O
I
S
T
TTL
IGNAL
YPE
Write Strobe/Read-Write Operation Identifier:
The exact function of this input pin depends upon which mode
the Microprocessor Interface has been configured to operate in,
as described below.
Intel-Asynchronous Mode – WR* - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the
Intel-Asynchronous Mode, then this input pin functions as the
WR* (Active-Low WRITE Strobe) input signal from the
Microprocessor. Once this active-low signal is asserted, then the
input buffers (associated with the Bi-Directional Data Bus pins,
D[7:0]) will be enabled. The Microprocessor Interface will latch
the contents on the Bi-Directional Data Bus (into the “target”
register or address location, within the XRT94L33) upon the
rising of this input.
Motorola-Asynchronous Mode - R/W* - Read/Write Operation
Identification Input Pin:
If the Microprocessor Interface is operating in the “Motorola-
Asynchronous” Mode, then this pin is functionally equivalent to
the “R/W*” input pin. In the Motorola Mode, a “READ” operation
occurs if this pin is held at a logic “1”, coincident to a falling edge
of the RD/DS* (Data Strobe) input pin.
PowerPC 403 Mode – R/W* - Read/Write Operation
Identification Input:
If the Microprocessor Interface is configured to operate in the
PowerPC 403 Mode, then this input pin will function as the
“Read/Write Operation Identification” input pin.
Anytime the Microprocessor Interface samples this input signal
at a logic “low” (while also sampling the CS* input pin “low”) upon
the rising edge of PCLK, then the Microprocessor Interface will
(upon the very same rising edge of PCLK) latch the contents of
the Address Bus (A]14:0]) into the Microprocessor Interface
circuitry, in preparation for this forthcoming READ operation. At
some point (later in this READ operation) the Microprocessor will
also assert the DBEN*/OE* input pin, and the Microprocessor
Interface will then place the contents of the “target” register (or
address location within the XRT94L33) upon the Bi-Directional
Dat Bus pins (D[7:0]), where it can be read by the
Microprocessor.
Anytime the Microprocessor Interface samples this input signal
at a logic high (while also sampling the CS* input pin at a logic
“low”) upon the rising edge of PCLK, then the Microprocessor
Interface will (upon the very same rising edge of PCLK) latch the
contents of the Address Bus (A[14:0]) into the Microprocessor
Interface circuitry, in preparation for the forthcoming WRITE
operation. At some point (later in this WRITE operation) the
Microprocessor will also assert the RD*/DS*/WE* input pin, and
the Microprocessor Interface will then latch the contents of the
Bi-Directional Data Bus (D[7:0]) into the contents of the “target”
register or buffer location (within the XRT94L33).
5
D
ESCRIPTION
XRT94L33
Rev.1.2.0.