XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 44

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
C14
STS1TXA_CK_0
TXSENDFCS_0
TXGFCCLK_0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
O
I
I
CMOS
TTL
TTL
STS-1 Transmit Telecom Bus Clock Input pin/Transmit
HDLC Control Block Send FCS Command Input pin –
Channel 0:
The exact function of this input pin depends upon whether the
STS-1 Telecom Bus Interface for Channel 0 has been enabled
or not.
If STS-1 Telecom Bus (Channel 0) has been enabled –
STS1TXA_CLK_0 - “STS-1 Transmit
Transmit Clock Input – Channel 0:
This input clock signal functions as the clock source for the
STS-1 Transmit Telecom Bus, associated with Channel 0. All
input signals (e.g., STS1TXA_ALARM_0, STS1TXA_D_0[7:0],
STS1TXA_DP_0, STS1TXA_PL_0, STS1TXA_C1J1_0) are
sampled upon the falling edge of this input clock signal.
This clock signal should operate at 19.44MHz. (For STS-3
mode) or 6.48MHz (for STS-1 mode)
If STS-1 Telecom Bus (Channel 0) has NOT been enabled:
If STS-1 Telecom Bus (Channel 0) has not been enabled, then
this particular pin can be configured to function in either of the
following roles.
TXSENDFCS_0 (Transmit HDLC Controller block Send
FCS Command Input – High Speed HDLC Controller Mode
Only)
The user’s terminal equipment is expected to control both this
input pin and the “TXSENDMSG_0” input pin during the
construction and transmission of each outbound HDLC frame.
This input pin permits the user to command the Transmit
HDLC Controller block to compute and insert the computed
FCS value into the back-end of the “outbound” HDLC frame as
a trailer.
If the user has configured the Transmit HDLC Controller to
compute and insert a CRC-16 value into the “outbound” HDLC
frame, then the terminal equipment is expected to pull this
input pin “high” for two periods of TxHDLCClk_0.
Likewise, if the user has configured the Transmit HDLC
Controller to compute and insert a CRC-32 value into the
“outbound” HDLC frame, then the terminal equipment is
expected to pull this input pin “high” for four periods of
TxHDLCClk_0.
TXGFCCLK_0 (Transmit GFC Nibble-Field Input Port clock
signal Input) – ATM Applications ONLY.
This pin only functions in this particular role if the XRT94L33
has been configured to operate in the ATM UNI Mode.
Note:
44
The user should tie this pin to GND the DS3/E3
Framer block has NOT been configured to operate
in the “High-Speed HDLC Controller” Mode.
xr
Telecom
Bus”