XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 14

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
AG25
P
AG3
V1
L4
L3
IN
#
LOSPECL_R
S
LOSPECL_P
LOSTTL_R
LOCKDET
IGNAL
LOSTTL
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
N
AME
I/O
O
I
I
I
I
LVPECL
LVPECL
S
CMOS
T
IGNAL
TTL
TTL
YPE
Loss of Optical Carrier Input – Primary:
The user is expected to connect the “Loss of Carrier” output
(from the Optical Transceiver) to this input pin.
If this input pin and the LOSPECL_P pin are pulled “high”, or if
both of these input pins are pulled “low”, tthen the Receive STS-
3 TOH Processor block will declare a “Loss of Optical Carrier”
condition.
Note:
Loss of Optical Carrier Input – Redundant:
The user is expected to connect the “Loss of Carrier” output
(from the Optical Transceiver) to this input pin.
If this input pin and the LOSPECL_R are pulled “high”, or if both
of these input pins are pulled “low”, then the Receive STS-3 TOH
Processor block will declare a “Loss of Optical Carrier” condition.
Note:
Loss of PECL Interface Input – Primary:
If this input pin is pulled “high”, then the Receive STS-3 TOH
Processor block will declare a “Loss of PECL Interface”
condition.
Note:
Loss of PECL Interface Input – Redundant:
If this input pin is pulled “high”, then the Receive STS-3 TOH
Processor block will declare a “Loss of PECL Interface”
condition.
Note:
Lock Detect Output Pin – Clock and Data Recovery PLL
Block
This output pin indicates whether the Clock and data recovery
PLL block has obtained lock to incoming STS-3/STM-1 signal or
not.
This pin pulses high if internal VCO frequency is within 0.05% of
external reference clock
This pin pulses low if internal VCO frequency is beyond 0.05% of
external reference clock, and Loss of lock is declared.
14
active.
Port” is active.
active. This input pin is inactive if the “Primary Port” is
active.
active.
Port” is active.
active. This input pin is inactive if the “Primary Port” is
active.
This input pin is only active if the “Primary Port” is
This input pin is only active if the “Redundant Port” is
This input pin is only active if the “Primary Port” is
This input pin is only active if the “Redundant Port” is
This input pin is inactive if the “Redundant
This input pin is inactive if the “Redundant
D
ESCRIPTION
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