XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 380
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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XRT94L33
Rev.1.2.0.
Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address = 0x1157)
Notes:
The “Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 and Byte 0” registers permit the user to write
The “default” value for the “B2 Error Threshold” is 0xFFFF.
S
Likewise, the user can specify the “SF Set Interval” period by writing the appropriate value into the “Receive
STS-3 Transport – Receive SF Set Monitor Interval – Byte 2, 1, and 0” registers, as depicted below.
Receive STS-3 Transport – Receive SF Set Monitor Interval – Byte 2 (Address = 0x1131)
Receive STS-3 Transport – Receive SF Set Monitor Interval – Byte 1 (Address = 0x1132)
Receive STS-3 Transport – Receive SF Set Monitor Interval – Byte 0 (Address = 0x1133)
Notes:
The “Receive STS-3 Transport – Receive SF Set Monitor Interval – Byte 2, Byte 1 and Byte 0” registers permit the user to
The actual length of time that the Receive STS-3 TOH Processor block will use (to accumulate B2 errors) to declare the
E
Suppose that the user writes in the value “0x000F” into the “Receive STS-3 Transport – Receive SF Burst
Error Tolerance” Registers; as depicted below.
PECIFYING THE
XAMPLE OF
B
B
B
B
R/W
R/W
R/W
R/W
in a 16-bit expression for the “B2 Error Threshold” for the “SF Burst Detector”.
write in a 24-bit expression for the “SF Set Interval”. The number that is written into these registers represents the
duration of the “SF Set Interval” period, in terms of SONET frame periods.
SF condition is value written into these registers.
IT
IT
IT
IT
1
0
0
0
7
7
7
7
D
EFINING THE
“SF S
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
6
6
6
6
ET
I
NTERVAL
SF D
ECLARATION
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
”
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
5
OF
SF_SET_MONITOR_WINDOW[23:16]
SF_SET_MONITOR_WINDOW[15:8]
SF_SET_MONITOR_WINDOW[7:0]
T
IME
SF_BURST_TOLERANCE[7:0]
C
RITERIA
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
4
4
4
4
– SF B
380
B
B
B
B
R/W
R/W
R/W
R/W
URST
IT
IT
IT
IT
1
0
0
0
3
3
3
3
D
ETECTOR
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
2
2
2
2
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
1
1
1
1
xr
B
B
B
B
R/W
R/W
R/W
R/W
IT
IT
IT
IT
1
0
0
0
0
0
0
0
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