XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 278

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Transmit SONET Path – Transmit F2 Byte Value Register (Address = 0xN9A3)
2.2.8.3.6.2
The Transmit SONET POH Processor block permits the user to specify the contents of the F2 byte, within the
“outbound” STS-1 SPE, via data applied to the “TxPOH_n” input pin.
The user can configure the Transmit SONET POH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “1” into Bit 7 (F2 Byte Insertion Type) within the “Transmit SONET Path –
SONET Control Register – Byte 0”, as depicted below.
Transmit SONET Path – SONET Control Register – Byte 0 (Address = 0xN983)
This step configures the Transmit SONET POH Processor block to use the “TxPOH_n” input port as the
source for the F2 byte, within each “outbound” STS-1 SPE.
Processor block will accept the value, corresponding to the F2 byte (via the “TxPOH_n” input port) and it will
write this data into the F2 byte position, within the “outbound” STS-1 SPE.
STEP 2 – Begin providing the values of the “outbound” F2 byte to the “TxPOH_n” input port.
The procedure for applying the F2 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the F2 byte value into the outbound STS-1 SPE data-stream
If the user intends to externally insert the F2 byte into the outbound STS-1 SPE, via the “TxPOH_n” input port,
then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD solution) to
do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 52.
Figure 52: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
F2 Insertion
B
B
Type
R/W
R/W
IT
IT
0
1
7
7
REI-P Insertion Type[1:0]
Setting and Controlling the Outbound F2 Byte via the “TxPOH_n Input Port”
B
B
R/W
R/W
IT
IT
0
0
6
6
B
B
R/W
R/W
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Transmit_F2_Byte_Value[7:0]
RDI-P Insertion Type[1:0]
B
B
R/W
R/W
IT
IT
0
0
4
4
278
B
B
R/W
R/W
IT
IT
0
0
3
3
In this mode, the Transmit SONET POH
Insertion
C2 Byte
B
B
Type
R/W
R/W
IT
IT
0
0
2
2
Unused
B
B
R/W
R/O
IT
IT
0
0
1
1
xr
Transmit
Enable
AIS-P
B
B
R/W
R/W
IT
IT
0
0
0
0