XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 387

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XRT94L33IB-L

Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheets

Specifications of XRT94L33IB-L

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 90 Illustration of the Functional Block Diagram of the XRT94L33 Mapper IC; with the Receive
STS-3c POH Processor block highlighted
The operation of the “Receive STS-3c POH Processor” block is discussed in some detail below.
2.3.2.1
As the XRT94L33 receives an incoming STS-3 data-stream, the Receive STS-3 TOH Processor block has the
responsibility of de-scrambling this incoming data-stream, and acquiring and maintaining frame
synchronization with the incoming STS-3 frames. Once these incoming STS-3 frames have been located; the
Receive STS-3c POH Processor block has the responsibility of locating and keeping track of the STS-3c
SPEs within this STS-3 data-stream.
As required by the SONET/SDH standards, the Receive STS-3c POH Processor blocks accomplish this by
monitoring the contents of each set of H1 and H2 bytes within the incoming STS-3 data-stream.
If a Given Channel is Receiving an STS-3c Signal
If a given channel is configured to receive an STS-3c signal, then each incoming STS-3 frame consists of a
single STS-3c SPE. The Receive STS-3c POH Processor block determines the location of this one STS-3c
SPE by the contents of the H1 and H2 byte the TOH of the incoming STS-3c data-stream.
The H1 and H2 Bytes within an STS-3c Signal
XRT95L34 – Channel 0
POINTER PROCESSING
STS-3/12
Interface
STS-3/12
Telecom
Interface
Interface
Interface
STS-3/12
STS-3/12
Telecom
STS-3/12
PECL
Block
Block
STS-3/12
PECL
Block
Block
Block
Bus
CDR
Bus
Block
CDR
Processor
Transmit
STS-3/12
Processor
Processor
Transmit
STS-3/12
STS-3/12
Processor
Receive
Block
STS-3/12
TOH
Microprocessor
Receive
Block
Block
TOH
TOH
Microprocessor
Block
TOH
Interface
Interface
Block
Block
Processor
Processor
Transmit
STS-3/12
STS-3/12
Processor
Processor
Transmit
Receive
STS-3/12
STS-3/12
Receive
Block
Block
POH
POH
Block
Block
Synthesizer
POH
POH
387
Synthesizer
Clock
Block
Clock
Block
Cell Processor
Cell Processor
Cell Processor
Cell Processor
Processor
Processor
Transmit
Processor
Processor
Transmit
Transmit
Receive
Receive
Transmit
Receive
Block
Block
Receive
Block
ATM
PPP
PPP
Block
Block
Block
ATM
Block
ATM
PPP
PPP
Block
ATM
POS-PHY
POS-PHY
UTOPIA/
Transmit
Interface
Transmit
Interface
Interface
Interface
UTOPIA
POS-PHY
POS-PHY
UTOPIA/
Transmit
Transmit
Receive
Receive
UTOPIA
Interface
Interface
Interface
Interface
Receive
Receive
Block
Block
Block
Block
Block
Block
Block
Block
XRT94L33
Rev.1.2.0.

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