XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 157

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 11 Timing Diagram of various Transmit UTOPIA Interface block signals, when the Transmit
UTOPIA Interface block is operating in the “Cell Level Handshaking” Mode
Notes regarding Figure 11:
1. The Transmit UTOPIA Data Bus is configured to be 16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data Bus, is expressed in terms of 16-bit words: W0 - W26.
2. The Transmit UTOPIA Interface Block is configured to handle 54 bytes/cell. Hence, figure 11 illustrates
the ATM Layer processor writing 27 words (W0 through W26) for each ATM cell.
In Figure 11, the ATM Layer processor starts to write in a new ATM cell, into the Transmit UTOPIA Interface
block, during clock edge #2. However, shortly after the ATM Layer processor has written in word W22 (at
clock edge # 24), the TxUClav output pin toggles “low”. In the “Cell-Level” Handshaking mode, this means
that ATM Layer processor is not permitted to write in the subsequent ATM cell (e.g., the ATM cell which is to
follow the one that is currently being written into the Transmit UTOPIA Interface block) into the Transmit
UTOPIA Interface block. Hence, the ATM Layer processor must complete writing in the current cell, and then
halt with any further write operations to the Transmit UTOPIA Interface block. Therefore, the ATM Layer
processor will proceed to write in Words W23 through W26 and then negate the TxUEnB* signal after clock
edge #28. At this point, the ATM Layer processor must wait until the TxUClav output pin toggles “high” once
again; before writing in the next ATM cell.
USING THE “TRANSMIT UTOPIA DE-SKEWING” PLL
2.2.1.3.4
The XRT94L33 can be configured to support either Single-PHY or Multi-PHY operation. Each of these
operating modes is discussed below.
2.2.1.3.5
The XRT94L33 permits the user to configure it to operate in either the “Single-PHY” or “Multi-PHY” Mode.
The user can configure the chip to operate in the “Single-PHY” Mode by setting Bit 6 (Multi-PHY Mode) to “0”;
as illustrated below.
TxUData [15:0]
TxUClav
TxUEnB *
TxUSoC
TxUClk
W26
Single PHY Operation
UTOPIA Modes of Operation (Single PHY and Multi-PHY operation)
1
W0
2
W1
3
W2
4
W22
24
157
W23
25
W24
26
W25
27
W26
28
X
29
30
X
XRT94L33
Rev.1.2.0.