XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 128

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Table 4 Pin Description of the Microprocessor Interface Signals while the Microprocessor Interface is
operating in the Motorola Mode
Rdy_Dt
1.3.2
The Microprocessor Interface block, within the XRT94L33 is very flexible and provides the following options to
the user.
•
•
•
Each of the options is discussed in detail below. Section _ will discuss Data Access (e.g., Programmed I/O
and Burst) Mode when interfaced to both Motorola-type and Intel-type µC/µP.
1.3.2.1
The user can configure the Microprocessor Interface, within the XRT94L33, to support a wide-variety of
Microprocessor Interface Modes. The user can accomplish this by setting the PType[2:0] input pins to the
appropriate setting as listed below.
Table 5 Settings for the PType[2:0] and the Corresponding Microprocessor Interface Modes
This revision of the XRT94L33 Data Sheet discusses the Motorola and Intel X86 Modes in detail. The
remaining Microprocessor Interface Modes will be discussed in a later revision of this data sheet.
RdB_D
ALE_A
WRB_
N
RW
P
AME
ck
S
S
IN
To interface the XRT94L33 to a µC/µP over an 8-bit-wide bi-directional data bus.
To interface the XRT94L33 to a wide variety of Microprocessor Interface types
To transfer data (between the XRT94L33 IC and the µC/µP) via the Programmed I/O Mode.
PT
YPE
000
001
010
011
100
101
E
I
[2:0]
E
NTERFACING THE
IN
QUIVALENT
S
NVIRONMENT
DTACK*
M
ELECTING THE
R/W*
OTOROLA
AS*
DS*
P
IN
68HC11, 8051, 80C188
Motorola – 68000 Family
Intel X86 Family
Intel i960
IDT3051/52
Power PC 403
A
XRT94L33
T
PPROPRIATE
YPE
O
I
I
I
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Address Strobe: This “active-low” signal is used to latch the contents on the
address bus input pins: A[14:0] into the Microprocessor Interface circuitry. The
contents of the Address Bus are latched into the XRT94L33 on the rising edge of
the ALE_AS signal. This signal can also be used to indicate the start of a burst
cycle.
Data Strobe: This signal latches the contents of the bi-directional data bus pins
into the Addressed Register within the XRT94L33 during a Write Cycle.
Read/Write* Input: When this pin is “high”, it indicates a Read Cycle. When this
pin is “low”, it indicates a Write cycle.
Data Transfer Acknowledge: The XRT94L33 asserts DTACK* in order to inform
the CPU that the present READ or WRITE cycle is nearly complete. The 68000
family of CPUs requires this signal from its peripheral devices, in order to quickly
and properly complete a READ or WRITE cycle.
TO THE
M
ICROPROCESSOR
M
µC/µP
ICROPROCESSOR
128
OVER VIA THE
I
NTERFACE
I
NTERFACE
M
D
ICROPROCESSOR
ESCRIPTION
M
M
ODE
ODE
I
NTERFACE
xr
B
LOCK