XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 371

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
At this point, the Receive STS-3 TOH Processor block will proceed to count B2 byte errors. If the Receive
STS-3 TOH Processor block is currently declaring the SD defect condition; it will now clear the SD defect
condition if it detects less than 8 B2 byte errors, within a given 256ms period.
Occurrences whenever the Receive STS-3 TOH Processor block clears the SD Defect Condition
Anytime the Receive STS-3 TOH Processor block clears the SD Defect Condition, then it will do the following.
•
Note:
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
•
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
2.3.1.14
The Receive STS-3 TOH Processor block is capable of declaring and clearing the SF condition. Further, the
Receive STS-3c TOH Processor block register set permits the user to define the “SF Declaration” and
“Clearance” criteria.
The Receive STS-3 TOH Processor block actually consists of two different “SF” Detectors.
•
•
The “Interval” SF Detector accumulates B2 errors over a long “user-defined” period of time. If the number of
B2 errors (accumulated over this “user-defined” period of time) exceeds a user-defined “threshold”, then the
“Interval” SF Detector will declare an “SF” Condition.
The “Burst” SD Detector functions similarly to that of the “Interval” SF Detector, in that it also accumulates B2
errors over a “user-defined” period of time. Further, the “Burst” SF Detector will declare the SF condition if the
number of B2 errors (accumulated over this “user-defined” period of time) exceeds a “user-defined” threshold,
then the “Burst” SD Detector will declare an “SF Condition”.
There are two main differences between the “Interval” SF Detector and the “Burst” SF Detectors.
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
RDI-L
B
B
RUR
It will generate the “Change of SD Defect Condition” Interrupt
It will set Bit 3 (SD Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” to “0”,
as depicted below.
R/O
The “Interval” SF Detector
The “Burst” SF Detector
IT
IT
0
0
7
7
The Receive STS-3 TOH Processor block will indicate that it is generating this interrupt by toggling the “INT*”
output pin “low” and be setting the “Change of SD Defect Condition Interrupt Status” bit to “1”, as depicted
below.
SF DECLARATION AND CLEARANCE CRITERIA
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
S1 Byte
Status
Defect
B
RUR
B
R/O
IT
IT
1
0
6
6
Detection of
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
RUR
B
R/O
IT
IT
0
0
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Status
B
Error
RUR
B
R/O
IT
IT
0
0
4
4
371
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Status
Error
B
RUR
B
R/O
IT
IT
0
0
3
3
LOF Defect
LOF Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/O
IT
IT
0
0
2
2
SEF Defect
SEF Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/O
IT
IT
0
0
1
1
XRT94L33
LOS Defect
LOS Defect
Change of
Condition
Declared
Interrupt
Status
Rev.1.2.0.
B
RUR
B
R/O
IT
IT
0
0
0
0