XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 415

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XRT94L33IB-L

Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheets

Specifications of XRT94L33IB-L

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
In numerous applications the payload portion of the incoming cells will scrambled by the remote terminal
equipment. These cells are scrambled in order to prevent the user data from mimicking framing or control
bytes. Therefore, the Receive ATM Cell Processor provides the user will the option of de-scrambling the
payload of these cells in order to restore the original content of the cell payload. (Please note that this cell de-
scrambler presumes that the cell payload were scrambled via the scrambling generating polynomial of x
1.) The user can configure this option by setting Bit 2 (De-Scramble Enable) within the “Receive ATM Cell
Processor – Receive ATM Control Register – Byte 0”, as depicted below.
Receive ATM Cell Processor Block – Receive ATM Control Register – Byte 0 (Address = 0xN703)
2.3.4.3
Idle Cell Filtering is actually achieved through the user of the Receive User Cell Filter. As a consequence, we
will now proceed to discuss the “Receive User Cell Filter”.
HEC Byte
Insert into
Enable
UDF1
B
R/W
IT
1
7
Receive UTOPIA
Interface Block
I
DLE
Main Data Path
HEC Status
into UDF2
RxFIFO
RxFIFO
Enable
C
B
R/W
ELL
IT
1
6
F
ILTER
HEC Byte Correction
B
R/W
IT
X
Calculation
Calculation
Threshold[1:0]
5
Parity
Block
Parity
Block
B
R/W
IT
X
4
De-Scrambler
Cell Payload
De-Scrambler
User Cell
Cell Payload
User Cell
Idle Cell
Filter
Block
415
Idle Cell
Block
Filter
Block
Filter
Block
Filter
UTOPIA
Receive
Parity -
B
ODD
R/W
IT
1
3
Cell Extraction
Cell Insertion
Cell Extraction
Cell Insertion
Processor
Processor
Verification
Processor
Processor
HEC Byte
Verification
Buffer/
Buffer/
HEC Byte
Buffer/
Buffer/
Block
B
Block
R/O
Receive GFC
Nibble-Field
Receive GFC
Nibble-Field
Output I/F
IT
0
Output I/F
2
Unused
Microprocessor
Microprocessor
STS-3c/STS-12c
Processor Block
B
R/O
From Receive
IT
Interface
0
Interface
Block
1
Block
POH
XRT94L33
Descramble
Enable
Rev.1.2.0.
B
R/W
IT
1
0
43
+

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