XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 192

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
STEP 4d – Write the contents of the fourth byte (of this new ATM cell) into the Transmit ATM Cell –
Insertion/Extraction Memory Register – Byte 0; as depicted below.
Transmit ATM Cell – Insertion/Extraction Memory Register – Byte 2 (Address = 0xNF17)
Note:
STEP 5 – Inform the “Cell Insertion Processor” that the very next 32-bit word to be written into the
“Cell Insertion Buffer” is NOT the first word of a new ATM cell.
This is accomplished by writing the value “0” into Bit 0 (Insertion Memory Write SoC), within the “Transmit
ATM Cell – Memory Control Register” as depicted below.
Transmit ATM Cell – Memory Control Register (Address = 0xNF13)
STEP 6 – Continue to write the contents of the remaining bytes of this ATM cell into the “Cell Insertion
Memory”.
This is accomplished by executing the procedure, outlined in STEP 4, repeatedly for 13 times.
Notes:
As the user writes the contents of an ATM cell into the “Transmit Cell Insertion Memory” they must follow the
mandated ATM cell byte format, as depicted in
B
B
R/W
R/O
1. .
2. If the user performs a READ operation to the “Transmit ATM Cell – Insertion/Extraction Memory
D7
IT
IT
0
7
7
In this case, the contents of the second byte (within this ATM cell) is of the value [D7, D6, D5, D4, D3, D2, D1,
Register – Bytes 3 through 0” they will NOT be reading out the contents of the Transmit Cell Insertion
Buffer. Instead, the user will be reading out data from the “Transmit Cell Extraction” buffer.
D0]
Unused
B
B
R/W
R/O
D6
IT
IT
0
6
6
B
B
R/W
R/O
D5
IT
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Insertion/Extraction Memory Data[7:0]
Extraction
RESET*
Memory
B
B
R/W
R/W
D4
IT
IT
1
4
4
192
Extraction
Memory
CLAV
B
B
R/W
R/W
D3
IT
IT
0
3
3
Insertion
RESET*
Memory
B
B
R/W
R/W
D2
IT
IT
1
2
2
Insertion
Memory
ROOM
B
B
R/W
R/W
D1
IT
IT
1
1
1
xr
Write SoC
Insertion
Memory
B
B
R/W
R/W
D0
IT
IT
0
0
0