XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 166

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.2.1.3.8
In this section, the various Multi-PHY Operations (e.g., polling and selection for writing) will be first discussed
for a “Conceptual Multi-PHY” System, and then later, specifically for the XRT94L33. When the XRT94L33 is
operating in the “Multi-PHY” mode, then the Transmit UTOPIA Interface block will automatically be configured
to support “polling”. “Polling” allows an ATM Layer processor (which is interfaced to several UNI devices) to
determine which UNIs are capable of receiving and handling additional ATM cell data, at any given time. The
manner in which the ATM Layer processor “polls” its UNI devices, (per the “Conceptual Multi-PHY” system)
follows.
Figure 15 An Illustration of the “Conceptual Multi-PHY System consisting of UNI Devices #1 and #2
2.2.1.3.9
Figure 26 depicts a “Multi-PHY” system consisting of a single ATM Layer processor and two (2) UNI devices,
which are designated as “UNI #1” and “UNI #2”. In this figure, both of the UNIs are connected to the ATM
Layer processor via a common “Transmit UTOPIA” Data Bus, a common “Receive UTOPIA” Data Bus, a
common “TxUClav” line, a common “RxUClav” line, as well as common TxUEnB*, RxUEnB*, TxUSoC and
RxUSoC lines. The ATM Layer processor will also be addressing both the Transmit and Receive UTOPIA
Interface blocks via a common “UTOPIA” address bus (Ut_Addr[4:0]) Therefore, the Transmit and Receive
UTOPIA Interface Blocks, within a given UNI might have different addresses; as depicted in Figure 26.
The UTOPIA Address values, that have been assigned to each of the Transmit and Receive UTOPIA
Interface blocks, within Figure 15, are listed below in Table 13.
TxAddr = 0x00 RxAddr = 0x01
ATM Layer Processor “polling” of the UNIs, in the Multi-PHY Mode
ATM Layer Processor “polling” in a Conceptual Multi-PHY System
TxAddr = 0x02 RxAddr = 0x03
UNI # 1
UNI # 2
TxUData[15:0]
RxUData[15:0]
TxUAddr[4:0]
RxUAddr[4:0]
TxUData[15:0]
TxUAddr[4:0]
RxUData[15:0]
RxUAddr[4:0]
TxUPrty
TxUEnb*
TxUSoC
TxUClav
RxUPrty
RxUEnb*
RxUSoC
RxUClav
TxUEnb*
TxUSoC
TxUClav
RxUEnb*
RxUClav
TxUPrty
RxUPrty
RxUSoC
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
166
RxData[15:0]
Rx_SoC_In
RxClav_In
TxData[15:0]
Tx_Parity
Tx_Ut_WR*
Tx_SoC_out
TxClav_In
Rx_Parity
Rx_Ut_Rd*
Ut_Addr[4:0]
ATM Layer Processor
xr