XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 239

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Transmit STS-3c Path – SONET Control Register – Byte 0 (Address = 0x1983)
This step configures the Transmit STS-3c POH Processor block to use the “TxPOH_n” input port as the
source for the F2 byte, within each “outbound” STS-3c SPE. In this mode, the Transmit STS-3c POH
Processor block will accept the value, corresponding to the F2 byte (via the “TxPOH_n” input port) and it will
write this data into the F2 byte position, within the “outbound” STS-3c SPE.
STEP 2 – Begin providing the values of the “outbound” F2 byte to the “TxPOH_n” input port.
The procedure for applying the F2 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the F2 byte value into the outbound STS-3c SPE data-stream
If the user intends to externally insert the F2 byte into the outbound STS-3c SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 38.
Figure 38: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 32 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
F2 Insertion
B
Type
R/W
IT
1
7
The “TxPOHIns_n” line (in Figure 38) is “dashed” because controlling this signal is not necessary if the user has
executed “STEP 1” above.
REI-P Insertion Type[1:0]
B
R/W
IT
0
6
XRT95L34 Device
B
R/W
IT
0
TxPOHEnable_n
5
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
RDI-P Insertion Type[1:0]
B
R/W
IT
0
4
239
B
R/W
IT
0
3
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
Insertion
C2 Byte
B
Type
R/W
IT
0
2
Unused
B
R/O
IT
0
1
XRT94L33
Transmit
Enable
AIS-P
Rev.1.2.0.
B
R/W
IT
0
0