XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 376

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.3.1.14.3
In this case, the user specifies two parameters to define the SF Clearance criteria.
• The maximum number of B2 errors (e.g., a B2 error-threshold) accumulated over a given “SF Clear
Interval” time period.
• The length (in terms of SONET frame periods) of this “SF Clear Interval” time period.
Once the user defines these parameters, then the Receive STS-3c TOH Processor block will begin to count
the cumulative number of B2 errors that it detects within a “sliding window” of time. The length of this “sliding
window of time” is dictated by the user-defined “SF Clear Interval” time period.
If the Receive STS-3c TOH Processor block is currently declaring the SF condition, and if continues to
detects more than the “B2 error threshold” number of B2 errors; within the “SF Clear Interval” of time, then it
will NOT clear the SF condition. Conversely, if the Receive STS-3c TOH Processor block detects less than
the “B2 error threshold” number of B2 errors, within the “SF Clear Interval” of time, then it will clear the SF
condition.
Specifying the “B2 Error Threshold” for Clearing SF
The user can specify the “B2 Error Threshold” by writing the appropriate value into the “Receive STS-3c
Transport – Receive SF Clear Threshold – Byte 1 and Byte 0” registers, as depicted below.
Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 1 (Address = 0x113A)
Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address = 0x113B)
Notes:
The “Receive STS-3 Transport – Receive SF Clear Threshold – Byte 1 and Byte 0” registers permits the user to write in a
The “default” value for the “B2 Error Threshold” is “0xFFFF”.
Declared
RDI-L
B
B
B
R/W
R/W
R/O
16-bit expression for the “B2 Error Threshold”.
IT
IT
IT
0
1
1
7
7
7
The SF (Signal Fail) Defect Clearance Criteria
S1 Unstable
B
B
B
R/W
R/W
R/O
IT
IT
IT
0
1
1
6
6
6
Unstable
B
B
B
APS
R/W
R/W
R/O
IT
IT
IT
0
1
1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
SF_CLEAR_THRESHOLD[15:8]
SF_CLEAR_THRESHOLD[7:0]
SF Detected
B
B
B
R/W
R/W
R/O
IT
IT
IT
1
1
1
4
4
4
376
SD Detected
B
B
B
R/W
R/W
R/O
IT
IT
IT
0
1
1
3
3
3
LOF Defect
Detected
B
B
B
R/W
R/W
R/O
IT
IT
IT
0
1
1
2
2
2
SEF Defect
Declared
B
B
B
R/W
R/W
R/O
IT
IT
IT
0
1
1
1
1
1
xr
LOS Defect
Declared
B
B
B
R/W
R/W
R/O
IT
IT
IT
0
1
1
0
0
0