XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 31

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
C10
D10
E11
C11
B10
C9
A8
B7
B9
TxPOHEnable_0
TxPOHEnable_1
TxPOHEnable_2
TxPOHFrame_0
TxPOHFrame_1
TxPOHFrame_2
TxPOHIns_0
TxPOHIns_1
TxPOHIns_2
O
O
I
T
RANSMIT
CMOS
CMOS
TTL
L
INE
/ S
YSTEM
Transmit Path Overhead Input Port – Frame Output pin:
These
“TxPOHEnable_n”,
function as the “Transmit Path Overhead Input Port”.
The exact function of these output pins depends upon whether
the user inserting POH or TOH data via the “TxPOH_n” input
pins.
If the user is only inserting POH data via these input pins:
The “TxPOH” port will pulse these output pins “high” whenever
it is ready to accept and process the J1 byte (e.g., the very first
POH byte) via this port.
Notes:
1.
2.
Transmit Path Overhead Input Port – Insert Enable Input
pin:
These input pins, along with “TxPOH_n”, “TxPOHEnable_n”,
“TxPOHFrame_n” and “TxPOHClk_n” function as the Transmit
Path Overhead (TxPOH) Input Port.
These input pins permit the user to enable or disable the
“TxPOH” input port.
If these input pins are pulled “high”, then the “TxPOH” port will
sample and latch data via the corresponding “TxPOH” input
pins, upon the falling edge of “TxPOHClk_n”.
Conversely, if these input pins are pulled “low”, then the
“TxPOH” port will NOT sample and latch data via the
corresponding “TxPOH” input pins.
Note:
Transmit Path Overhead Input Port – POH Indicator
Output pin:
These output pins, along with “TxPOH_n”, “TxPOHIns_n”,
“TxPOHFrame_n”
“Transmit Path Overhead (TxPOH) Input Port”.
These output pins will pulse “high” anytime the “TxPOH” port is
ready to accept and process POH bytes.
will be “low” at all other times.
31
S
The externally circuitry can determine whether the
“TxPOH” port is expecting the A1 byte or the J1 byte, by
checking the state of the corresponding “TxPOHEnable”
output pin. If the “TxPOHEnable_n” output pin is “LOW”
while the “TxPOHFrame_n” output pin is “HIGH”, then the
“TxPOH” port is ready to process the A1 (TOH) bytes.
If the “TxPOHEnable_n” output pin is “HIGH” while the
“TxPOHFrame_n” output pin is “HIGH”, then the “TxPOH”
port is ready to process the J1 (POH) bytes.
IDE
I
output
NTERFACE
setting will be overridden if the user has configured
the “Transmit SONET/STS-1 POH Processor” or
“Transmit STS-1 TOH Processor” blocks to accept
certain POH or TOH overhead bytes via the external
port.
If the “TxPOHIns_n” input pin is pulled “LOW”, this
pins,
P
and
INS
“TxPOHIns_n”
“TxPOHClk_n”
along
with
and
the
function
These output pins
“TxPOHClk_n”
XRT94L33
“TxPOH_n”,
as
Rev.1.2.0.
the