XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 187

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.2.6.8
The Transmit ATM Cell Processor block consists of a “Transmit Cell Insertion Buffer/Processor” block. Figure
24 presents the functional block diagram of the Transmit ATM Cell Processor block with the “Transmit Cell
Insertion Buffer/Processor” block highlighted.
Figure 24: Illustration of the Transmit ATM Cell Processor block Functional Block Diagram, with the
“Transmit Cell Insertion Buffer/Processor” block highlighted
The Transmit Cell Insertion Buffer/Processor block permits the user to load the contents of an “outbound”
ATM cell into the “Transmit Cell Insertion Buffer” via the Microprocessor Interface. Once this cell has been
loaded into the “Transmit Cell Insertion Buffer”, then it will be transmitted to the remote terminal equipment
(via the Transmit Data Path) whenever the “TxFIFO” (within the Transmit UTOPIA Interface block) is depleted
of user cells.
transmission of OAM cells.
The Format of ATM Cell Data that is written into the “Transmit Cell Insertion” Buffer
As the user loads the contents of an ATM cell into the “Transmit Cell Insertion” Buffer (via the Microprocessor
Interface), they will be expected to write this ATM cell data into a 32 bit wide register/buffer interface. As a
consequence, the user must write in 56-byte size ATM cells into the “Transmit Cell Insertion” buffer.
The byte format of this 56 byte ATM cell is as illustrated below in Figure 25.
Transmit UTOPIA
T
Interface Block
HE
TxFIFO
An example of an application where this feature would be useful is in the loading and
TxFIFO
T
RANSMIT
Main Data Path
C
ELL
I
NSERTION
Generator
Checker
Generator
Checker
Parity
Idle Cell
Block
Parity
Idle Cell
Block
B
UFFER
/P
User Cell
Calculation
HEC Byte
User Cell
Calculation
Insertion
HEC Byte
Filter
Block
ROCESSOR
Insertion
187
Filter
Block
Block
Block
&
&
Cell Extraction
Cell Insertion
Cell Extraction
Transmit GFC
Cell Insertion
Cell Payload
Processor
Transmit GFC
Processor
Nibble-Field
Cell Payload
Scrambler
Processor
Processor
Nibble-Field
Buffer/
Buffer/
Input Port
Scrambler
Buffer/
Buffer/
Input Port
Block
Block
Block
Block
Microprocessor
Microprocessor
Processor Block
SONET/STS-3c
To Transmit
Input Port
Interface
Interface
TxGFC
Block
Block
POH
XRT94L33
Rev.1.2.0.