XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 425

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive ATM Cell – Memory Control Register (Address = 0xN713)
Note:
STEP 2 – Check and see if an ATM cell exists in the “Receive Cell Extraction Buffer”
This can be accomplished by one of two approaches.
• Polling approach
• Interrupt-driven approach
Each of these approaches is described below.
Executing STEP 2 using the Polling Approach
The user can determine whether or not a cell is available, within the “Receive Cell Extraction Buffer” by
testing the state of Bit 3 (Extraction Memory CLAV) within the Receive ATM Cell – Memory Control Register;
as depicted below.
Receive ATM Cell – Memory Control Register (Address = 0xN713)
If Bit 3 is set to “1”, then the “Receive Cell Extraction Buffer” contains an ATM cell that needs to be read. At
this point, the user should proceed on to STEP 3.
Conversely, if Bit 3 is set to “0”, then the “Receive Cell Extraction Buffer” does not contain an ATM cell that
needs to be read. At this point, the Microprocessor Interface should continue to poll the state of this bit-field
and wait until this bit-field toggles to “1”.
Executing STEP 2 using the Interrupt-Driven Approach
In order to reduce or eliminate the Microprocessor Overhead of continuously polling the state of Bit 3, the user
can use the “Receive Cell Extraction” Interrupt feature, within the chip. If the Microprocessor invokes this
feature, then the XRT94L33 will generate an interrupt anytime a new cell has been received and loaded into
the “Receive Cell Extraction Buffer”.
The user can enable the “Cell Extraction” Interrupt by setting Bit 5 (Cell Extraction Interrupt Enable), within the
“Receive ATM Cell Processor – Interrupt Enable” Register to “1” as indicated below.
B
B
R/O
R/O
IT
IT
0
0
7
7
This step should typically be performed upon power-up, prior to processing any ATM cell traffic through the
XRT94L33. This step is not necessary after the first cell has been read from the “Receive Cell Extraction
Buffer” following a power cycle to the chip.
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
6
6
B
B
R/O
R/O
IT
IT
0
0
5
5
Extraction
Extraction
RESET*
RESET*
Memory
Memory
B
B
0->1
R/W
R/W
IT
IT
1
4
4
425
Extraction
Extraction
Memory
Memory
CLAV
CLAV
B
B
R/W
R/W
IT
IT
X
0
3
3
Insertion
Insertion
RESET*
RESET*
Memory
Memory
B
B
R/W
R/W
IT
IT
1
1
2
2
Insertion
Insertion
Memory
Memory
ROOM
ROOM
B
B
R/W
R/W
IT
IT
1
1
1
1
XRT94L33
Write SoC
Write SoC
Insertion
Insertion
Memory
Memory
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
0
0
0
0