XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 130

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Figure 4 Behavior of Microprocessor Interface signals during an “Intel-type” Programmed I/O Read
Operation
1.3.3.2
Whenever an Intel-type µC/µP wishes to write a byte or word of data into a register or buffer location, within
the XRT94L33, it should do the following.
1. Assert the ALE_AS (Address Latch Enable) input pin by toggling it “high”. When the µC/µP asserts the
ALE_AS input pin, it enables the “Address Bus Input Drivers” within the XRT94L33 chip.
2. Place the address of the “target” register or buffer location within the XRT94L33, on the Address Bus input
pins, A[14:0].
3. While the µC/µP is placing this address value onto the Address Bus, the Address Decoding circuitry (within
the user’s system) should assert the CS* input pin of the XRT94L33 by toggling it “low”. This step enables
further communication between the µC/µP and the XRT94L33 Microprocessor Interface block.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate “Address Setup” time);
the µC/µP should toggle the ALE_AS input pin “low”. This step causes the XRT94L33 to “latch” the contents
of the “Address Bus” into its internal circuitry. At this point, the address of the register or buffer location within
the XRT94L33, has now been selected.
5.
WRB_RW (Write Strobe) input pin “low”. This action also enables the “bi-directional” data bus input drivers of
the XRT94L33.
6. The µC/µP should then place the byte or word that it intends to write into the “target” register, on the bi-
directional data bus, D[7:0].
7. After waiting the appropriate amount of time, for the data (on the bi-directional data bus) to settle; the
µC/µP should toggle the WRB_RW (Write Strobe) input pin “high”. This action accomplishes two things:
block.
Figure 5 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
during an “Intel-type” Programmed I/O Write Operation.
WRB_RW
WRB_RW
WRB_RW
ALE_AS
ALE_AS
RDB_DS
RDB_DS
Rdy_Dtck
Rdy_Dtck
D[7:0]
D[7:0]
A[14:0]
A[14:0]
CS*
CS*
Next, the µC/µP should indicate that this current bus cycle is a “Write” Operation; by toggling the
a. It latches the contents of the bi-directional data bus into the XRT94L33 Microprocessor Interface
b. It terminates the write cycle.
T
HE
I
NTEL
M
ODE
W
RITE
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
C
Address of Target Register
Address of Target Register
YCLE
Not Valid
Not Valid
130
Valid
Valid
xr