XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 249

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for _ periods of “TxPOHClk_n” to elapse).
Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g., the most
significant bit) of the “outbound” Z4 byte onto the “TxPOH_n” input pin, upon the very next falling edge of
“TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c POH Processor” block
circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the H4 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
2.2.7.3.10
The Transmit STS-3c POH Processor block permits the user to control the value of the H4 byte by either of
the following options.
• Setting and controlling the “outbound” Z5 Byte via Software
• Setting and controlling the “outbound” Z5 Byte via the “TxPOH Input Port”
The details and instructions for using either or these features are presented below.
2.2.7.3.10.1
The Transmit STS-3c POH Processor block permits the user to specify the contents of the Z5 byte, within the
“outbound” STS-3c SPE via software command.
The user can configure the Transmit STS-3c POH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “0” into Bit 0 (Z5 Insertion Type) within the “Transmit STS-3c Path – SONET
Control Register – Byte 1”, as depicted below.
Transmit STS-3c Path – SONET Control Register – Byte 1 (Address = 0x1982)
This step configures the Transmit STS-3c POH Processor block to read out the contents of the “Transmit
STS-3c Path – Transmit Z5 Byte Value” register; and load this value into the Z5 byte position within each
“outbound” STS-3c SPE.
STEP 2 – Write the desired byte value (for the outbound Z5 byte) into the “Transmit STS-3c Path –
Transmit Z5 Byte Value” register.
The bit-format of this register is presented below.
B
R/O
IT
0
7
The “TxPOHIns_n” line (in Figure 43) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the Z4 byte is the 8th byte within the POH.
executed “STEP 1” above.
SUPPORT/HANDLING OF THE Z5 BYTE
Setting and Controlling the Outbound Z5 Byte via Software
B
R/O
IT
0
6
Unused
B
R/O
IT
0
5
B
R/O
IT
0
4
249
Z5 Insertion
Type
B
R/W
IT
0
3
Z4 Insertion
B
Type
R/W
IT
0
2
Z3 Insertion
B
Type
R/W
IT
0
1
XRT94L33
H4 Insertion
Rev.1.2.0.
B
Type
R/W
IT
X
0