XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 410

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
3. It will correct the “Single-Bit” Error within this particular ATM cell.
4. The “HEC Byte Verification” Block will transition into the “Detection” Mode.
If the HEC Byte Verification Block detects a Multi-Bit Error within the Header bytes of an incoming
ATM Cell:
1.
Processor block will indicate that it is declaring the “Detection of Uncorrectable HEC Byte Error” Interrupt, by
doing the following.
2. It will increment the “Receive ATM Cell Processor Block – Receive ATM Cell with Uncorrectable HEC Byte
Error Count” Registers. This is a 32-bit RESET-upon-READ register that resides at Address Locations
0xN734 through 0xN737. The bit format of these registers is presented below.
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 3 (Address = 0xN734)
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 2 (Address = 0xN735)
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 1 (Address = 0xN736)
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 0 (Address = 0xN737)
B
RUR
B
RUR
B
RUR
B
RUR
B
a. Toggling the “INT*” output pin “low”.
b. Setting Bit 2 (Detection of Uncorrectable HEC Byte Error Interrupt Status), within the “Receive ATM
It will generate the “Detection of Uncorrectable HEC Byte Error” Interrupt.
IT
IT
IT
IT
IT
0
0
0
0
7
7
7
7
7
Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
B
RUR
B
RUR
B
RUR
B
RUR
B
IT
IT
IT
IT
IT
0
0
0
0
6
6
6
6
6
Received Cells with Uncorrectable HEC Byte Error Count[31:24]
Received Cells with Uncorrectable HEC Byte Error Count[23:16]
Received Cells with Uncorrectable HEC Byte Error Count[15:8]
Received Cells with Correctable HEC Byte Error Count[7:0]
B
RUR
B
RUR
B
RUR
B
RUR
B
IT
IT
IT
IT
IT
0
0
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
5
5
B
B
B
B
B
RUR
RUR
RUR
RUR
IT
IT
IT
IT
IT
0
0
0
0
4
4
4
4
4
410
B
RUR
B
RUR
B
RUR
B
RUR
B
IT
IT
IT
IT
IT
0
0
0
0
3
3
3
3
3
B
B
B
B
B
RUR
RUR
RUR
RUR
IT
IT
IT
IT
IT
0
0
0
0
2
2
2
2
2
The Receive ATM Cell
B
RUR
B
RUR
B
RUR
B
RUR
B
IT
IT
IT
IT
IT
0
0
0
0
1
1
1
1
1
xr
B
RUR
B
RUR
B
RUR
B
RUR
B
IT
IT
IT
IT
IT
0
0
0
0
0
0
0
0
0