XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 418
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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XRT94L33
Rev.1.2.0.
ENABLING/DISABLING THE RECEIVE USER CELL FILTER
The Receive ATM Cell Processor block permits the user to either enable or disable each of the four Receive
User Cell Filters. The user can accomplish this by writing the appropriate data into Bit 3 (User Cell Filter
Enable), within the “Receive ATM Filter Control – Byte 0” register; as depicted below.
Receive ATM Filter # 0, # 1, # 2, # 3 Control – Byte 0 (Address = 0xN743, 0xN753, 0xN763, 0xN773)
Note:
Setting this bit-field to “1” enables the corresponding Receive User Cell Filter. Conversely, setting this bit-field
to “0” disables the “Receive User Cell Filter”.
If a given Receive User Cell Filter is enabled, then it will perform action on all incoming ATM cells, based
upon the settings of the remaining register bits within this register; and that within both the “Receive ATM
Filter Control – Pattern” and “Receive ATM Filter Control – Check” registers. Conversely, if the given Receive
User Cell Filter is disabled, then all User Cells will pass through the Receive User Cell Filter, and towards the
“Parity Calculation & Insertion” block without any such actions performed on these cells.
SELECTING THE RECEIVE USER CELL FILTER ACTION
The Receive ATM Cell Processor block permits the user to specify the action that the User Cell Filter will take
on each cell, that meets certain “User-Defined” Filtering requirements. The user can accomplish this by
setting Bits 2 (Copy Cell Enable) and 1 (Discard Cell Enable), within the Receive ATM Filter Control – Byte 0”
Register; to the appropriate values. These two bit-fields are highlighted below.
Receive ATM Filter # 0, # 1, # 2, # 3 Control – Byte 0 (Address = 0xN743, 0xN753, 0xN763, 0xN773)
Bit 2 – Copy Cell Enable
This bit-field permits the user to configure the “Receive User Cell” filter (within the Receive ATM Cell
Processor block) to either replicate (copy) or not replicate a given cell that complies with the “user-defined”
filtering requirements. All copied cells are routed to the “Receive ATM Cell Processor Extraction Memory”,
where their contents can be read out by the user via the Microprocessor Interface.
Setting this bit-field to “1” configures the Receive User Cell Filter to copy all cells that comply with the “user-
cell” filter requirements, and to route these cells to the “Receive ATM Cell Processor – Extraction Memory”.
Conversely, setting this bit-field to “0” configures the Receive User Cell Filter to NOT copy these cells, and
NOT route these cells to the “Receive ATM Cell Processor – Extraction Memory.
Bit 1 – Discard Cell Enable
This bit-field permits the user to configure the “Receive User Cell” filter (within the Receive ATM Cell
Processor block) either discard or not discard a given cell that complies with the “user-defined” filtering
B
B
R/O
R/O
IT
IT
0
0
7
7
As the bit-format table for the “Receive ATM Filter Control – Byte 0” register implies, each of the four (4) Receive
User Cell Filters can be individually enabled or disabled. Further, each of these four Receive User Cell Filters
can be individually configured to either “Copy” or “Discard” cells (or both).
B
B
R/O
R/O
IT
IT
0
0
6
6
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
B
B
R/O
R/O
IT
IT
0
0
4
4
418
Filter Enable
Filter Enable
User Cell
User Cell
B
B
R/W
R/W
IT
X
IT
1
3
3
Copy Cell
Copy Cell
Enable
Enable
B
B
R/W
R/W
IT
IT
X
0
2
2
Discard Cell
Discard
Enable
B
B
R/W
R/W
Cell
IT
IT
X
0
1
1
xr
Filter Sense
Filter Sense
User Cell
User Cell
B
B
R/W
R/W
IT
IT
X
0
0
0
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