XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 356

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address = 0x1109)
2.3.1.6
The Receive STS-3 TOH Processor block is capable of detecting the REI-L indicator, within the incoming
STS-3 data-stream. As the Receive STS-3 TOH Processor block receives a given STS-3 data-stream, it will
monitor the contents within the M1 byte. The bit-format of the M1 byte is presented below in Figure 88.
Figure 88 Bit format of the M1 Byte
The role of the REI-L bit-fields was described in some detail, in Section _. This section indicates that the
remote terminal equipment will set the “REI-L” value (within the M1 byte) to “0” during “un-erred” conditions.
However, the remote terminal equipment will typically set the “REI-L” value to a value (ranging from “1” to
“24”) during “erred” conditions.
If the Receive STS-3 TOH Processor block receives an STS-3 frame, that contains a “non-zero” value of REI-
L, then it will do the following.
Note:
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
Note:
Change of
SF Defect
Condition
Interrupt
Status
B
B
RUR
R/O
15. It will generate the “Detection of REI-L Error” Interrupt.
16. It will increment the “Receive STS-3 Transport – REI-L Error Count” Registers
IT
IT
0
0
7
7
The Receive STS-3 TOH Processor block will indicate this by, pulling the “INT*” output pin “LOW” and by setting
These registers are actually 32-bit registers, which are located at Direct Address locations 0xNA19 through
B
Bit 5 (Detection of REI-L Error Interrupt Status), within the “Receive STS-3 Transport – Interrupt Status Register
– Byte 0” to “1” as depicted below.
0xNA1C. The bit-format of these registers is presented below.
IT
DETECTING AND FLAGGING REI-L (LINE – REMOTE ERROR INDICATOR) EVENTS
1
Change of
SD Defect
Condition
Interrupt
Status
B
B
RUR
R/O
IT
IT
0
0
6
6
B
IT
2
Detection of
REI-L Error
Interrupt
Status
B
B
RUR
R/O
IT
IT
0
1
B
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
IT
3
Unused
Detection of
Interrupt
B2 Byte
B2 Error Count (REI-L)
Status
B
B
Error
RUR
R/O
B
IT
IT
0
0
IT
4
4
4
356
Detection of
Interrupt
B1 Byte
B
Status
B
B
Error
RUR
R/O
IT
IT
IT
0
0
5
3
3
LOF Defect
Change of
B
Condition
Interrupt
IT
Status
B
B
RUR
R/O
6
IT
IT
0
0
2
2
B
AIS-L Defect
SEF Defect
Change of
Change of
IT
Condition
Condition
Interrupt
Interrupt
Status
Status
7
B
RUR
B
RUR
IT
IT
0
0
1
1
xr
B
IT
LOS Defect
Change of
Change of
Condition
8
Condition
Interrupt
Interrupt
Defect
Status
Status
RDI-L
B
RUR
B
RUR
IT
IT
1
0
0
0