XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 354

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
•
2.3.1.5
According to Telecordia GR-253-CORE, a Line Terminating Equipment must declare the RDI-L (Line –
Remote Defect Indicator) condition whenever it determines that bits 6, 7 and 8 (within the K2 byte) of the
incoming STS-3c data-stream, are set the pattern [1, 1, 0] for five consecutive STS-3c frames.
Figure 87 presents the illustration of the “RDI-L Declaration/Clearance” State Machine Diagram that is used
by the Receive STS-3 TOH Processor block within the XRT94L33.
Figure 87 Illustration of the “RDI-L Declaration/Clearance” State Machine Diagram
2.3.1.5.1
The Receive STS-3c TOH Processor block is capable of declaring and clearing the RDI-L defect condition. If
the Receive STS-3 TOH Processor block receives at least five consecutive STS-3 frames, in which bits 6, 7
and 8 (within the K2 byte) are set to the “[1, 1, 0]” pattern, then it will declare the RDI-L defect condition. The
Receive STS-3 TOH Processor block will indicate that it is declaring the RDI-L defect condition by doing all of
the following.
•
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
Declared
Defect
RDI-L
B
The corresponding Receive ATM Cell Processor block will declare the LCD (Loss of Cell Delineation)
defect condition.
It will set Bit 7 (RDI-L Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” to
“1” as illustrated below.
IT
7
Receive STS-3/STS-12 TOH Processor block
Receives five (5) consecutive frames in which bits
6, 7, and 8 (within the K2 byte) are NOT set to the
Pattern [1, 1, 0]
RDI-L DECLARATION AND CLEARANCE CRITERIA
How the Receive STS-3 TOH Processor Block Declares the RDI-L Defect Condition
Unstable
D
S1 Byte
Defect
B
IT
l
6
d
Defect is
Defect is
Cleared
RDI-L
Cleared
RDI-L
K1, K2 Byte
D
Unstable
Defect
B
IT
l
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
d
SF Defect
Declared
B
IT
4
Receive STS-3/STS-12 TOH Processor
block receives five (5) consecutive frames
In which bits 6, 7 and 8 (within the K2 byte)
are set to the pattern [1, 1, 0]
354
SD Defect
Declared
B
IT
3
Defect is
Declared
Defect is
Declared
LOF Defect
RDI-L
Declared
RDI-L
B
IT
2
SEF Defect
Declared
B
IT
1
xr
LOS Defect
Declared
B
IT
0