XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 40

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
AG21
AF19
AE17
TXHDLC_CLK_0/
TXHDLC_CLK_1/
TXHDLC_CLK_2/
STUFFCNTL_0/
STUFFCNTL_1/
STUFFCNTL_2/
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
I/O
TTL/CMOS
Transmit PLCP Processor Block – Nibble Trailer Stuff
Control Input pin/Transmit High-Speed HDLC Controller
Input Interface – Clock Output pin – Channel n:
The exact function of this input pin depends upon (1) whether
the XRT94L33 has been configured to operate in the ATM
UNI/PLCP Mode and (2) whether a given DS3/E3 Framer
block/Channel has been configured to operate in the “High-
Speed HDLC Controller” Mode, as described below.
ATM UNI Mode - STUFFCNT_n: Transmit PLCP Processor
block Nibble-Trailer Stuff Control Input pin – Channel n -
STUFFCNT_n:
This pin only functions in this particular role if the XRT94L33
has been configured to operate in the ATM UNI Mode. For
more information on this pin operating in this mode, please
see the XRT94L33 Pin Description for ATM UNI/PPP
Applications.
High-Speed HDLC Controller Mode – Transmit HDLC
Controller Input Interace Block - Clock output signal –
Channel n – TxHDLCClk_n:
This output signal functions as the “demand” clock for the
Transmit High-Speed HDLC Controller Input Interface block,
associated with the DS3/E3 Framer blocks. Whenever the
user pulls the “Snd_Msg_n” input pin “high” then the Transmit
High-Speed HDLC Controller block will begin to sample and
latch the contents of the “TxHDLCDat[7:0] input pins upon the
falling edge of this clock signal.
configure their terminal equipment circuitry to output (or place)
data onto the “TxHDLCDat[7:0] bus upon the rising edge of
this clock signal.
Since the Transmit HDLC Controller block is sampling and
latching 8-bits of data at a given time, it may be assumed that
the frequency of the TxHDLC_CLK_n output signal is either
34.368MHz/8 or 44.736MHz/8. In general, this presumption is
true. However, because the Transmit HDLC Controller block
is also performing “Zero-Stuffing” of the user data that it
accepts from the Terminal Equipment, the frequency of this
signal may be slower.
Note:
40
The user should tie this pin to GND if the DS3/E3
Framer block has NOT been configured to operate
in the “High-Speed HDLC Controller” Mode.
The user is advised to
xr