XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 440

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Selecting the Cell Size (Number of Octets per Cell)
The XRT94L33 permits the user to select the number of octets per cell that the Receive UTOPIA Interface
block will process. Specifically, the user has the following cell size options.
• If the UTOPIA Data Bus width is set to 8 bits then the user can choose:
• If the UTOPIA Data Bus width is set to 16 bits, then the user can choose:
The user makes his/her selection by writing the appropriate data into bits 1 and 0 (Cell_Size_Sel[1:0]) within
the Receive UTOPIA Control Register, as depicted below.
Receive UTOPIA Control Register – Byte 0, Address = 0x0403
The following table presents the relationship between the value of this bit and the number of octets/cell that
the Receive UTOPIA Interface block will process.
Table 21 The Relationship between the contents of Bits 1 and 0 (Cell_Size_Sel[1:0]) within the
Transmit UTOPIA Control Register, and the number of octets per cell that will be processed by the
Transmit UTOPIA Interface blocks per assertion of TxUSOC
Once the user has implemented his/her selection for the cell size, then the Receive UTOPIA Interface block
will be configured to process the “Cell Size” number of octets per cell.
CELL LEVEL HANDSHAKING
ATM Forum documentation refers to both “Cell Level” and “Octet-Level” handshaking.
XRT94L33 only supports the “Cell-Level” Handshaking mode. Octet-level handshaking is NOT supported. In
the “Cell-Level” Handshaking mode, when the RxUClav output is at a logic “1”, it means that the Rx FIFO
contains at least one complete ATM cell of data that is available for reading by the ATM Layer Processor.
When RxUClav toggles from “high” to “low”, it indicates that Rx FIFO contains less than one complete ATM
cell. The ATM Layer processor is expected to monitor the RxUClav output, and quickly respond and read the
Rx FIFO, whenever the RxUClav output signal is asserted.
Figure 110 presents a timing diagram that illustrates the behavior of various Receive UTOPIA Interface block
signals, when the Receive UTOPIA Interface block is operating in the “Cell-Level” Handshaking Mode.
UTOPIA
C
Level
B
R/W
ELL
IT
1
52 bytes (with no HEC byte in the cell), or
53 bytes (with either a dummy or actual HEC byte in the cell)
7
_S
52 bytes (with no HEC byte in the cell), or
54 bytes (with either a dummy or actual HEC byte, and a stuff byte in the cell)
IZE
00
01
10
11
_S
EL
Multi-PHY
[1:0]
Mode
B
R/W
IT
0
6
Polling Enable
53 bytes/cell (only value if the Transmit UTOPIA Data Bus Width = 8 bits)
Back-to-Back
B
R/W
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Direct Status
Access
B
R/W
IT
0
N
4
UMBER OF
440
52 bytes/cell
54 bytes/cell
Unused
Receive UTOPIA Data Bus
B
YTES
B
R/W
IT
1
/C
3
Width[1:0]
ELLS
B
R/W
IT
1
2
Cell_Size_Sel[1:0]
xr
B
R/W
IT
X
1
However, the
B
R/W
IT
X
0