XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 408

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Figure 99 State Machine Diagram of the HEC Byte Error Correction/Detection Algorithm
The “Correction” State
When the HEC Byte Verification Block is operating within the “Correction” State, within the “HEC Byte Error
Correction/Detection” Algorithm, then cells that contain single bit errors (within the Header bytes) will be
corrected. However, cells with multiple bit errors are discarded, unless configured by the user.
Note:
Receive ATM Cell Processor Block – Receive ATM Control Register – Byte 1 (Address = 0xN702)
If the HEC Byte Verification Block is operating in the “Correction State” then it will do all of the following
anytime it detects any incoming ATM cells that contain header byte errors.
B
R/O
IT
0
7
The user can configure the Receive ATM Cell Processor block to retain cells that contain multi-bit errors, by
setting Bit 2 (Uncorrectable HEC Byte Error Discard), within the “Receive ATM Cell Processor Block – Receive
ATM Control Register – Byte 1” register, to “0”, as depicted below.
No Error
Detected
Unused
B
R/O
IT
0
6
Correction
Mode
B
R/O
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Multi-bit Error Detected
Single-bit Error Detected
for M consecutive cells
Extraction
(Cell Discarded)
Enable
No Error Detected
(Cell Corrected)
B
GFC
R/W
IT
0
4
408
Correction
HEC Byte
Enable
B
R/W
IT
1
3
Alpha consecutive cells with incorrect
HEC bytes (to HUNT state)
Detection
Mode
Uncorrectable
Error Discard
HEC Byte
B
R/W
IT
0
2
Polynomial
(Cell Discarded)
Error Detected
Addition
COSET
B
R/W
IT
1
1
xr
Regenerate
HEC Byte
Enable
B
R/W
IT
0
0