XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 210

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
STEP 3 – After the Microprocessor has determined which of the four Transmit ATM Cell Processor
blocks is the “Interrupting” block within the XRT94L33, then it should read out the contents of the
corresponding “Transmit ATM Cell Processor – Interrupt Status Register”.
This will permit the Microprocessor to identify the exact cause of the interrupt request, from the Transmit ATM
Cell Processor block.
presented below.
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
If the cause of this interrupt is the “Transmit Cell Extraction” Interrupt, then Bit 5 (Cell Extraction Interrupt
Status) within the “Transmit ATM Cell Processor – Interrupt Status Register” will be set to “1” as depicted
above.
Recommended Subsequent Action
Once the Microprocessor Interface has identified this particular interrupt as being the “Transmit Cell
Extraction” Interrupt, then the user is advised to read out the contents of the “Transmit Cell Extraction” Buffer.
The procedure for reading out the contents of the “Transmit Cell Extraction” Buffer is presented in Section
4.2.2.4.
The Transmit Cell Insertion Interrupt
The Transmit ATM Cell Processor block will generate the “Transmit Cell Insertion” interrupt anytime the
“Transmit Cell Insertion” Processor transmits an ATM cell into the “Transmit Data Path” (thereby “freeing up”
space for another ATM cell to be written into the “Cell Insertion” Buffer). The purpose of this interrupt is to
notify the Microprocessor that the “Transmit Cell Insertion” Buffer contains sufficient available space to accept
at least one more ATM cell from the Microprocessor.
Enabling the “Transmit Cell Insertion” Interrupt
The user can enable the “Cell Insertion” Interrupt by executing the following steps.
B
R/O
IT
0
7
Unused
B
R/O
IT
0
6
The bit-format of “Transmit ATM Cell Processor – Interrupt Status” Register is
Extraction
Interrupt
Status
B
RUR
Cell
IT
1
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Insertion
Interrupt
Status
B
RUR
Cell
IT
0
4
210
Extraction
Overflow
Interrupt
Memory
Status
B
RUR
Cell
IT
0
3
Cell Insertion
Overflow
Interrupt
Memory
Status
B
RUR
IT
0
2
Detection of
HEC Byte
Interrupt
Status
B
Error
RUR
IT
0
1
xr
Detection of
Parity Error
Interrupt
Status
B
RUR
IT
0
0